30837fd24f
nv40: fix a couple of typos
2007-11-20 20:56:47 +11:00
f01e305e98
nv40: use native Z24_S8 format for zeta buffer
2007-11-20 19:10:58 +11:00
85d626508a
Add support for Z24_S8 to GL state tracker.
2007-11-20 19:09:47 +11:00
04fcee96b1
nv40: track pipe const id
2007-11-20 19:08:33 +11:00
b4c813313a
nv40: remove use of temps for KILP, implement KIL
2007-11-20 15:34:26 +11:00
060127af38
nouveau: update to latest header
2007-11-20 13:22:11 +11:00
c4f9fbb57f
optimize earlyz_quad(), add comments, remove unneeded #includes
2007-11-19 18:16:07 -07:00
0204cbb4f1
optimize linear_interpolation(), perspective_interpolation() functions
2007-11-19 18:15:21 -07:00
3821d15e06
[965] Add INTEL_DEBUG=fall debugging output.
2007-11-19 15:29:31 -08:00
27674c4135
[965] Convert DBG macro to use FILE_DEBUG_FLAG like i915.
2007-11-19 15:28:26 -08:00
87373e3072
fix some texture format assertions, etc
2007-11-19 10:37:54 -07:00
22a374fc3f
fix out-of-bounds array index (ix=-1)
2007-11-19 09:55:47 -07:00
7f718f0476
Implement early depth test.
...
Early depth test is enabled when depth test is enabled and
alpha test is disabled and fragment shader does not write
depth.
The early-z is implemented by moving the depth test stage
just before the fragment shader stage and prepending it
with an earlyz stage, introduced with this commit.
The earlyz stage prepares the quad->outputs.depth for
the following depth test stage by interpolating Z position,
just as the fragment shader would do.
2007-11-18 18:20:20 +00:00
c7c6253169
nouveau: m2mf fallback path for region copies.
2007-11-18 23:08:33 +11:00
f940603037
nv40: fix thinko == fix 3d textures
2007-11-18 22:12:50 +11:00
a1d622190f
nv40: support TXP again
2007-11-18 21:47:18 +11:00
3ab26c864c
nv40: some very rough guesses for get_paramf()
2007-11-18 17:59:45 +11:00
bc449c28c6
nouveau: oops, when'd that disappear..
2007-11-18 17:49:30 +11:00
2f33b5b56e
nouveau: Very rough cut at gallium winsys + nv40 pipe driver.
2007-11-18 17:34:06 +11:00
ca7f68a7cf
Fix typo
2007-11-17 15:39:36 +00:00
dec60d33b2
Proper fence reference counting.
2007-11-17 15:39:36 +00:00
f00a64999c
[intel] Add 965 support to shared intel_blit.c
...
This requires that regions grow a marker of whether they are tiled or not,
because fence (surface) registers are ignored by the 965 2D engine.
2007-11-16 17:29:30 -08:00
9b461d4d02
[i915] Pass static region names in so debugging says more than "static region".
2007-11-16 16:18:30 -08:00
34a00276c7
more convenient debug code
2007-11-16 17:13:26 -07:00
aa880bdfa0
Reimplement glRasterPos using the private 'draw' module.
2007-11-16 17:13:01 -07:00
6a1154bab0
adjustments so st_feedback_draw_vbo() can be used for glRasterPos
2007-11-16 17:12:22 -07:00
5ef6803b7a
[intel] Move additional code to be shared from intel_context.h to intel/.
2007-11-16 16:05:11 -08:00
5cdf3972de
[intel] Move intel_tex.h into place, forgotten in the previous commit.
2007-11-16 15:51:34 -08:00
8775bf475b
[965] Add batchbuffer decode for several more packets.
2007-11-16 15:44:11 -08:00
a66413874d
[intel] Fix typos in intel_chipset.h macros.
2007-11-16 15:36:18 -08:00
3bd07ba0d4
[i915] Add INTEL_DEBUG=sync debug flag to wait for fences after making them.
2007-11-16 15:36:18 -08:00
f7e0513d70
[i915] Reenable batchbuffer debug under INTEL_DEBUG=bat.
2007-11-16 15:36:18 -08:00
152aa6350d
[intel] Add some doxygen notes on what the bufmgr_fake block members mean.
2007-11-16 15:36:18 -08:00
c29e9e534e
[intel] Add a simple relocation cache to the fake buffer manager.
...
This is required for 965 performance, as it avoids a lot of repeated data
uploads of the state caches due to surface offsets in them.
2007-11-16 15:36:18 -08:00
4bc625e378
[intel] Assert against 0-sized buffers in dri_bufmgr_fake.c.
...
They shouldn't be created, and this often helps catch stupid issues.
2007-11-16 15:36:18 -08:00
00eb5635c6
[intel] Add support for multiple levels of relocation in bufmgr_fake.
...
This is required for 965 support, which has relocations in other places than
just the batchbuffer.
2007-11-16 15:36:18 -08:00
df3c530bed
[i915] Push locking in intelClearWithTris down inside meta_draw_poly.
...
The lock coverage and checks for cliprects were unneeded since the batchbuffer
will have INTEL_BATCH_CLIPRECTS anyway. It appeared to be a leftover from
intelClearWithBlit.
This makes the locking requirements of i915 meta_draw_quad match i965
meta_draw_quad.
2007-11-16 15:36:18 -08:00
8211b20026
added z/s keys to reset/step rotation
2007-11-16 15:19:05 -07:00
fb69fe58a0
Only emit texcoords for enabled units. Enable/disable units with 0..7 keys.
...
Also, asst. clean-ups.
2007-11-16 15:19:05 -07:00
95f066fc54
note problem with fragment coord Y orientation
2007-11-16 10:39:08 -07:00
f361edae5d
added a clip-bypass flag to rasterizer state
2007-11-16 09:31:25 -07:00
90dd0cb822
Include fences in the i915simple winsys interface.
2007-11-15 17:07:50 +00:00
96ba38a450
fix bogus assumption if ddx has set up surface reg for z buffer
...
this is wrong since even if ddx has not set up a surface reg to cover the z
buffer we should pretend it has on those rv100 chips since they presumably do
not do z buffer tiling if not using hyperz, so we can use linear addressing
just the same. Doesn't seem to fix #13080 , but it's wrong anyway and the bug
almost certainly broke newer non-tcl chips.
2007-11-15 01:13:16 +01:00
dab7c810e9
fix position invariant vertex programs for sw-tnl
...
do the same math as for fixed function pipe, including
user clip planes.
(mostly resurrected from the dead t_vb_arbprogram.c code)
2007-11-15 00:52:38 +01:00
f6ab1347d6
remove dependency on libGLU
2007-11-12 08:02:09 -07:00
b87ce5be82
add glw.pc.in to tarball list, remove from DEPEND_FILES
2007-11-12 07:51:55 -07:00
9bf5da906f
i965: correct the opcode of XY_SETUP_BLT_CMD. fix bug #12730
2007-11-12 10:20:26 +08:00
578641941f
test that point/line/quad rendering hits the right pixels
2007-11-09 17:02:51 -07:00
9724dc1ac7
[i915] Remove old frontbuffer rotation hack.
...
This was replaced in previous releases of xserver/dri/libGL by reporting the
damage to the frontbuffer so that the server and driver could handle it
appropriately.
2007-11-09 15:05:56 -08:00
7d4b89a2b3
[intel] By default, output batchbuffer decode to stderr like other debug info.
2007-11-09 14:27:33 -08:00
Ben Skeggs