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10829 Commits

Author SHA1 Message Date
Rob Clark 8023ede00a ci: Remove per-driver wayland-dEQP-EGL xfails 
Since these are not driver specific and have been added to
all-skips.txt, remove them from per-driver CI expectations.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26779>
 2023-12-22 11:13:23 +00:00
Matt Turner f2c97440f2 intel: Only validate inst compaction if debugging a shader stage 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26791>
 2023-12-22 03:16:32 +00:00
Jonathan Gray fbb9ce0140 intel/common: add directory prefix to intel_gem.h include 
Otherwise common/intel_gem.h may get included instead of
common/i915/intel_gem.h when building in a different directory.

Fixes: e050a00b9f ("intel/common: Move i915 files to i915 folder")
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26784>
 2023-12-21 16:37:04 +00:00
David Heidelberg 16af090908 ci/lava: separate HW definitions from SW 
Reviewed-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26722>
 2023-12-20 10:15:44 +00:00
Jianxun Zhang 1b8a07095d intel/isl: Add Gfx 12.x RC_CCS_CC into modifier scores 
Add RC_CCS_CC drm modifiers of TGL, DG2 and MTL into
the list with a higher score than RC_CCS modifiers.

Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Acked-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25651>
 2023-12-19 13:57:16 +00:00
Jianxun Zhang ed45f95b51 intel/vulkan: Add COMPRESSED_CLEAR state in layout translation 
The added state is for RC_CCS_CC modifiers that support fast
clear.

Fix:
vkcube: ../src/intel/vulkan/anv_image.c:2686: anv_layout_to_aux_state:
Assertion `!"" "unexpected isl_aux_state"' failed.

Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Acked-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25651>
 2023-12-19 13:57:16 +00:00
Jianxun Zhang 24b4f9c3ba intel/vulkan: Update comment of a workaround of modifiers 
Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Acked-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25651>
 2023-12-19 13:57:16 +00:00
Jianxun Zhang 12f0715787 intel/vulkan: Correct a comment about an offset in fast clear 
Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Acked-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25651>
 2023-12-19 13:57:16 +00:00
Jianxun Zhang 9c5a28d919 intel/vulkan: Use the last 2 dwords of clear color struct 
Refer to the comments added in the code, we now take the
last 2 dwords in the clear color struct to store the fast
clear type and the first compression state.

Suggested by Nanley Chery <nanley.g.chery@intel.com>

Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Acked-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25651>
 2023-12-19 13:57:16 +00:00
Jianxun Zhang 82f47acb16 intel/vulkan: Remove private binding on fast clear region 
To support modifiers with fast clear color, the region
should be able to export along with main surface, so we
remove the private binding in such case.

Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Acked-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25651>
 2023-12-19 13:57:16 +00:00
Jianxun Zhang 91a10251b9 intel/vulkan: Import aux state tracking buffer 
Pass down the offset of aux state tracking buffer
of an imported image from the layout provided from
the application.

Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Acked-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25651>
 2023-12-19 13:57:16 +00:00
Jianxun Zhang 1d5326b30e intel/vulkan: Specify offset when creating aux state tracker 
Allow aux state tracking buffer created with different offsets,
in order to support importing images with drm modifiers. We
will always need to calculate the size of an imported fast
clear region because Vulkan spec defines:
VUID-VkImageDrmFormatModifierExplicitCreateInfoEXT-size-02267
For each element of pPlaneLayouts, size must be 0

Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Acked-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25651>
 2023-12-19 13:57:16 +00:00
Jianxun Zhang a26d62df6b intel/vulkan: Allow modifiers supporting fast clear 
Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Acked-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25651>
 2023-12-19 13:57:16 +00:00
Jianxun Zhang ab6f1b1d57 intel/vulkan: Report clear color in subresource layout 
To support drm modifiers with fast clear features, this
change reports the layout of the region back to application.
Because it tracks all levels and layers in that plane, the
whole region is reported back regardless the level and
layer are being queried.

Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Acked-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25651>
 2023-12-19 13:57:16 +00:00
Jianxun Zhang f280b6e8d5 intel: Move mod_plane_is_clear_color() into isl 
We are going to reuse this helper in anv driver and
also rename it.

Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Acked-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25651>
 2023-12-19 13:57:16 +00:00
Jianxun Zhang 3b885926e9 intel/isl: Add a debug option to override modifer list 
Developers can limit supported modifers to a single
modifier provided in INTEL_MODIFIER_OVERRIDE environment
variable for debug purposes. For example, setting it
makes Vulkan CTS only run modifier tests against the
specified modifier instead of all modifiers in production
code.

Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Acked-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25651>
 2023-12-19 13:57:16 +00:00
Sviatoslav Peleshko 8f8cde4c60 intel/fs: Don't optimize DW*1 MUL if it stores value to the accumulator 
Fixes: a8b86459 ("i965/fs: Optimize a * 1.0 -> a.")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9570
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25710>
 2023-12-19 13:32:23 +00:00
Kenneth Graunke 49b8ccbcdc intel/fs: Drop opt_register_renaming() 
In the past, multiple writes to a single register were pretty common,
but since we've transitioned to NIR, and leave the IR in SSA form for
everything not captured in a phi-web, the pattern of generating new
temporary registers at each step is a lot more common.

This pass isn't nearly as useful now.  Across fossil-db on Alchemist,
this affects only 0.55% of shaders, which fall into two cases:

- Coarse pixel shading pixel-X/Y setup.  There are a few cases where
  we write a partial calculation into a register, then have a second
  instruction read that as a source and overwrite it as a destination.
  While we could use a temporary here, it doesn't actually help with
  register pressure at all, since there's the same amount of values
  live at both instructions regardless.  So while this pass kicks in,
  it doesn't do anything useful.

- Geometry shader control data bits (5 shaders total).  We track masks
  for handling EndPrimitive in a single register across the program,
  and apparently in some cases can split the live range.  However, it's
  a single register...only in geometry shaders...which use EndPrimitive.
  None of them appear to be in danger of spilling, either.  So this tiny
  benefit doesn't seem to justify the cost of running the pass.

So, just throw it out.  It's not worth keeping.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26343>
 2023-12-19 11:07:18 +00:00
Kenneth Graunke 866205d4d7 intel/fs: Allow omitting the destination of A64 untyped atomics 
This works exactly the same as the other atomics and the missing
destination is already handled in lower_logical_sends().

Only affects 2 shaders in fossil-db (in Cyberpunk 2077), but the
cycle count drops by 4.23%.  Nice to have in place at any rate.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26343>
 2023-12-19 11:07:18 +00:00
Jordan Justen 30faa7a483 anv, iris, intel/genxml: Update 3DSTATE_HS for xe2 
Update 3DSTATE_HS programming for xe2

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26600>
 2023-12-18 15:41:31 +00:00
Jordan Justen 8ba9988858 anv, iris, intel/genxml: Update 3DSTATE_GS for xe2 
Update 3DSTATE_GS programming for xe2

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26600>
 2023-12-18 15:41:31 +00:00
Jordan Justen 1bc7c966f4 intel/batch_decoder: Update 3DSTATE_PS decoding for xe2 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26600>
 2023-12-18 15:41:31 +00:00
Jordan Justen a659b1f0c0 anv, blorp, iris, intel/genxml: Update 3DSTATE_PS_EXTRA for xe2 
Update 3DSTATE_PS_EXTRA programming for xe2

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26600>
 2023-12-18 15:41:31 +00:00
Jordan Justen 5548e6a478 anv, blorp, iris, intel/genxml: Update 3DSTATE_VS for xe2 
Update 3DSTATE_VS programming for xe2

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26600>
 2023-12-18 15:41:31 +00:00
Jordan Justen f170995e66 anv, blorp, iris: Update 3DSTATE_PS programming for xe2 
Rework:
 * Jordan: Move code into intel_update_ps_state()

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26600>
 2023-12-18 15:41:30 +00:00
Zhang, Jianxun 80d9294d2d intel/isl: update 3DSTATE_STENCIL_BUFFER (xe2) 
Update xml file and adjust driver code to compile.

Signed-off-by: Zhang, Jianxun <jianxun.zhang@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26600>
 2023-12-18 15:41:30 +00:00
Zhang, Jianxun 2a49a598ce intel/genxml: update 3DSTATE_DEPTH_BUFFER instruction (xe2) 
Signed-off-by: Zhang, Jianxun <jianxun.zhang@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26600>
 2023-12-18 15:41:30 +00:00
Jordan Justen 99eadc2ecb intel/genxml: Add UNIFIED_COMPRESSION_FORMAT enum for xe2 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26600>
 2023-12-18 15:41:30 +00:00
Zhang, Jianxun 2c41811808 intel/genxml: update 3DSTATE_WM_HZ_OP instruction (xe2) 
The depth clear value is provided from 3DSTATE_WM_HZ_OP now.

Signed-off-by: Zhang, Jianxun <jianxun.zhang@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26600>
 2023-12-18 15:41:30 +00:00
Zhang, Jianxun 5d4a995294 intel/genxml: Remove 3DSTATE_CLEAR_PARAMS instruction (xe2) 
Signed-off-by: Zhang, Jianxun <jianxun.zhang@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26600>
 2023-12-18 15:41:30 +00:00
Rohan Garg 9512f61cd8 iris,isl: Adjust driver for several commands of clear color (xe2) 
The xe2 xml will be updated in following commits. Commit message
has been updated by Jianxun.

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26600>
 2023-12-18 15:41:30 +00:00
Dave Airlie f76f4be301 intel/compiler: move gen5 final pass to actually be final pass 
This got broken by the register conversion, this pass needs to be
after all the others.

Fixes: ce75c3c3fe ("intel: Switch to intrinsic-based registers")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26731>
 2023-12-18 07:24:37 +00:00
José Roberto de Souza ba6faeb974 anv: Remove libdrm usage from Xe KMD backend 
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26699>
 2023-12-15 20:40:49 +00:00
José Roberto de Souza dea6c82437 intel: Sync xe_drm.h final part 
Sync xe_drm.h with commit a8ff56e160bb ("drm/xe/uapi: Remove reset uevent for now").

This is the last xe_drm.h uAPI break.

The only relevant change for ANV and Iris is that now VM bind uAPI
is asynchronous only so I had to bring back the syncobj creation, wait
and destruction.

Is still in the Xe port TODO list to make VM binds truly asynchronous.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26699>
 2023-12-15 20:40:49 +00:00
Sagar Ghuge 2ac78b5096 anv: Enable blitter engine unconditionally on ACM+ 
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26703>
 2023-12-15 20:10:53 +00:00
Tapani Pälli 2f25679b3f anv: cleanup, use intel_needs_workaround instead of is_dg2 
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26666>
 2023-12-15 06:13:41 +00:00
Tapani Pälli 7ff8f79a88 anv/hasvk/drirc: change anv_assume_full_subgroups to have subgroup size 
Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26385>
 2023-12-15 05:28:51 +00:00
Caio Oliveira bfc953add7 intel/compiler: Use C helpers to access builtin types 
Remove usage of C++ static members as they are going to be removed.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26658>
 2023-12-15 03:09:19 +00:00
Lionel Landwerlin 6a92af158d anv: wait for CS write completion before executing secondary 
Got a error state on DG2 with a jump to secondary. The secondary is
empty and padded with MI_NOOPs to workaround the CS prefetching.
According to the error state, the return jump address from the
secondary to the primary is 0x0. The ACTHD register value is 0x10, so
it seems that the command streamer indeed jumped to 0x0 and hanged on
a few dwords after that.

The return address should have been set edited by a previous
MI_STORE_DATA_IMM instruction. So it appears it did not complete in
time for the command stream to catch it. On Gfx12+ this can happend if
we do not set ForceWriteCompletionCheck.

This change also takes the opportunity to remove the padding MI_NOOPs
at the end of secondaries on Gfx12+ by using disabling the prefetching
just before jumping into secondaries and reenabling it at the
beginning of each secondary.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26665>
 2023-12-14 11:28:31 +02:00
Sagar Ghuge 46f5359238 anv: Invalidate aux map for copy/video engine 
Make sure to invalidate the aux map table for copy/video engines on
platforms that has the aux map.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9231

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26409>
 2023-12-14 00:53:15 +00:00
Sagar Ghuge 108f880986 anv: Handle video/copy engine queue initialization 
We don't need to setup any state for video/copy usually but platform
that supports the aux map, we need to init the aux map by programming
equivalent registers.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26409>
 2023-12-14 00:53:15 +00:00
Sagar Ghuge 2aea09c8de intel/genxml: Add BCS/VD0 aux table base address register 
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26409>
 2023-12-14 00:53:15 +00:00
Chris Spencer ebc3032245 anv/android: Only limit advertised Vulkan version in strict mode 
Signed-off-by: Chris Spencer <spencercw@gmail.com>
Acked-by: Chia-I Wu <olvaffe@gmail.com>
Acked-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25101>
 2023-12-13 20:09:37 +00:00
Sagar Ghuge a4947f7bd8 intel/fs: Adjust destination size for load ubo on Xe2+ 
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26639>
 2023-12-13 19:06:21 +00:00
Sagar Ghuge e0ce94318b intel/fs: Adjust destination size for global load constant on Xe2+ 
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26639>
 2023-12-13 19:06:21 +00:00
Sagar Ghuge 11fea46bdc intel/fs: Adjust destination size for image size intrinsic 
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26639>
 2023-12-13 19:06:21 +00:00
Sagar Ghuge c426553658 intel/compiler: Adjust assertion in lower_get_buffer_size() for Xe2 
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26639>
 2023-12-13 19:06:21 +00:00
Lionel Landwerlin d761871761 isl: drop AUX-TT CCS alignment with INTEL_DEBUG=noccs 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26644>
 2023-12-13 17:40:38 +00:00
Rohan Garg 40c6e54ce7 anv: rename anv_create_companion_rcs_command_buffer to anv_cmd_buffer_ensure_rcs_companion 
We can now drop any checks for companion_rcs_cmd_buffer before calling
anv_create_companion_rcs_command_buffer.

Ensure that anv_cmd_buffer_ensure_rcs_companion callee's have the proper
error handling.

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26648>
 2023-12-13 11:19:07 +00:00
Lionel Landwerlin d376d8c5ea anv: promote EXT_calibrated_timestamps to KHR 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26632>
 2023-12-13 09:39:08 +00:00