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intel/fs: Adjust destination size for global load constant on Xe2+

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Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26639>
This commit is contained in:
Sagar Ghuge
2023-09-26 13:43:44 -07:00
committed by Marge Bot
parent 11fea46bdc
commit e0ce94318b
1 changed files with 4 additions and 2 deletions
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src/intel/compiler/brw_fs_nir.cpp
+4 -2
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@@ -6517,7 +6517,8 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb,
}
case nir_intrinsic_load_global_constant_uniform_block_intel: {
const unsigned total_dwords = ALIGN(instr->num_components, REG_SIZE / 4);
const unsigned total_dwords = ALIGN(instr->num_components,
REG_SIZE * reg_unit(devinfo) / 4);
unsigned loaded_dwords = 0;
const fs_builder ubld1 = bld.exec_all().group(1, 0);
@@ -6543,7 +6544,8 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb,
srcs[A64_LOGICAL_ENABLE_HELPERS] = brw_imm_ud(0);
ubld.emit(SHADER_OPCODE_A64_UNALIGNED_OWORD_BLOCK_READ_LOGICAL,
retype(byte_offset(packed_consts, loaded_dwords * 4), BRW_REGISTER_TYPE_UD),
srcs, A64_LOGICAL_NUM_SRCS)->size_written = block_bytes;
srcs, A64_LOGICAL_NUM_SRCS)->size_written =
align(block_bytes, REG_SIZE * reg_unit(devinfo));
increment_a64_address(ubld1, address, block_bytes);
loaded_dwords += block;