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485 Commits

Author SHA1 Message Date
Marcin Ślusarz 11612d81b7 intel/genxml: fix width of 3DSTATE_TASK_CONTROL.MaximumNumberofThreadGroups 
Fixes: 3567d47f3e ("intel/genxml: Inline the BODY structs into the instructions")
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19412>
 2022-11-02 08:56:53 +00:00
Nanley Chery 0fa540ef61 iris: Reduce use of RHWO optimization (Wa_1508744258) 
Implement Wa_1508744258:

   Disable RHWO by setting 0x7010[14] by default except during resolve
   pass.

Disable the RCC RHWO optimization at all times except when resolving
single sampled color surfaces. MCS partial resolves are done via
software (i.e., not via a HW bit) and so are not expected to need this
workaround.

Reviewed-by: Mark Janes <markjanes@swizzler.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19360>
 2022-10-31 23:26:06 +00:00
Dylan Baker 3395b40b37 intel/genxml: use Path.replace instead of unlink and rename 
Suggested-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18955>
 2022-10-12 10:59:15 -07:00
Dylan Baker ede03c99db intel/genxml: use a main() function 
So we have less stuff in the global namespace

Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18955>
 2022-10-12 10:59:12 -07:00
Dylan Baker 0ac3b6f671 intel/genxml: split the processing code up 
Instead of crewating output or validating in the process code, just
process, then let main handle the rest

Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18955>
 2022-10-12 10:59:09 -07:00
Dylan Baker 8c8a1966ab intel/genxml: reprocess xml with elementree output 
This makes two relatively small changes, first it addes the encoding to
the xml delcaration, and switches the quote style. Second, it changes
the final newline. These seemed minor enough to not warrent patches to
make the old wrter do the same thing as the new writer.

Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18955>
 2022-10-12 10:59:06 -07:00
Dylan Baker 9a185d78ca intel/genxml: use ElementTree.write and .indent 
This removes a bunch of hand-written code, and allows for fewer corner
cases. The resulting code has some minor differences (no empty newlines
and the encoding is declared in the xml declaration)

Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18955>
 2022-10-12 10:59:03 -07:00
Dylan Baker b876f4daa9 intel/genxml: re-process with extra whitespace removed 
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18955>
 2022-10-12 10:59:01 -07:00
Dylan Baker db8c6590e0 intel/genxml: remove newlines between xml islands 
When we move to using etree to print this it won't have them, so this
minimizes the diff further.

Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18955>
 2022-10-12 10:58:58 -07:00
Dylan Baker 9acd459bee intel/genxml: re-process with space before /> 
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18955>
 2022-10-12 10:58:56 -07:00
Dylan Baker b150b89e61 intel/genxml: write a space before the '/>` closing tag 
ElementTree.write will do this, and we want to minimize the diff when we
switch from our own writer to the builtin one.

Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18955>
 2022-10-12 10:58:49 -07:00
Tapani Pälli 1cf1a94f97 intel: revert preemption disable via VFG changes 
This register will not be whitelisted and this change will be
done in kernel instead.

This change reverts commits d5d4604a, ddcd6b38, 27c5b93d.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18897>
 2022-10-04 10:38:49 +00:00
Dylan Baker 1f0a0a46d9 meson: run genxml sort tests 
Reviewd-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18917>
 2022-10-01 14:03:49 -07:00
Dylan Baker 3f0da1bbfa intel/genxml: run gen_sort_tags on all of the xml 
Reviewd-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18917>
 2022-10-01 14:03:49 -07:00
Dylan Baker 106da29196 intel/genxml: add a validation mode to gen_sort_tags 
Reviewd-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18917>
 2022-10-01 14:03:49 -07:00
Dylan Baker 1386fd6a7b intel/genxml: add 'nonzero' to gen_sort_tags 
which was added in ebe2a2b5f6.

Reviewd-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18917>
 2022-10-01 14:03:49 -07:00
Dylan Baker 92857fd5c9 intel/genxml: don't overwrite the input of gen_sort_tags in place 
otherwise we can be left with garbage

Reviewd-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18917>
 2022-10-01 14:03:49 -07:00
Dylan Baker c0aeeb93a8 intel/genxml: remove unused variable in gen_sort_tags.py 
Reviewd-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18917>
 2022-10-01 14:03:49 -07:00
Dylan Baker 27d89a673d intel/genxml: use a not in {x, y} instead of a != x or a != y 
It's faster, less code, and more idiomatic

Reviewd-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18917>
 2022-10-01 14:03:49 -07:00
Dylan Baker 4fd2e15855 intel/genxml: add type annotations to gen_sort_tags.py 
let static analysis help us out

Reviewd-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18917>
 2022-10-01 14:03:49 -07:00
Dylan Baker 3f9fe21988 intel/genxml: don't use parens with python assert statement 
assert is a statement in python, not a function. Useing parens with it
leads to madness, because assert takes two arguments in the form `assert
expression: bool, message: str`. With parens though it's tempting to
write `assert(expression, message)`, which results in an assert that is
*always* true, because a non-empty tuple (which is what is written) is
*never* false.

Reviewd-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18917>
 2022-10-01 14:03:49 -07:00
Dylan Baker f286451ada intel/genxml: use a set for lookups 
Python will pre-compute the set since it's const, and the performance of
a set search is significantly better than that of a list search

Reviewd-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18917>
 2022-10-01 14:03:49 -07:00
Dylan Baker e04ece53d7 intel/genxml: use a single pattern for res 
regex is expensive, do less of it.

Reviewd-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18917>
 2022-10-01 14:03:49 -07:00
Kenneth Graunke 98bd984977 intel/genxml: Add XY_FAST_COLOR_BLT 
We'll need to use this for VkCmdFillBuffer on transfer queues.

Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15183>
 2022-09-28 08:41:35 +00:00
Jason Ekstrand 5814436159 anv: Set up the memory-backed FIFO buffer 
v2: Fix incorrect goto (Caio)
    Comment 3DSTATE_BTD programming (Caio)

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16970>
 2022-09-28 05:38:36 +00:00
Lionel Landwerlin a5e5e6aa0f genxml: add missing no duplicate anyhit flag 
This mirrors the VK_GEOMETRY_NO_DUPLICATE_ANY_HIT_INVOCATION_BIT_KHR
enum of VkGeometryFlagBitsKHR. Purely here for documentation.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16970>
 2022-09-28 05:38:36 +00:00
Tapani Pälli d5d4604aa6 intel/genxml: add VFG_PREEMPTION_CHICKEN_BITS register 
This can be used to disable batch preemption on DG2+ either
completely or with selected primitive topologies.

Commit adds bit explicitly for Polygon, Trifan and LineLoop
topologies for Wa_14015207028.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18456>
 2022-09-14 10:01:23 +00:00
Jason Ekstrand c52d5acf15 util,intel: Pull the bit packing helpers from genxml to a common header 
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18062>
 2022-08-30 04:28:34 +00:00
Jason Ekstrand d82cea5fc3 genxml: Add BVH data structures 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17908>
 2022-08-05 11:51:31 +00:00
Marcin Ślusarz f4386b81e6 intel: fix typos found by codespell 
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17191>
 2022-06-27 10:20:55 +00:00
Kenneth Graunke b05ac36f01 intel/genxml: Add SAMPLER_MODE bits for enabling Small PL on Icelake 
This enables a lower power mode in the sampler hardware in certain
common scenarios.  On Tigerlake, SAMPLER_MODE is not programmable by
userspace but the kernel already sets this bit for us.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15628>
 2022-04-11 19:17:07 +00:00
Kenneth Graunke e3defe7ae7 intel/genxml: Delete SAMPLER_MODE register definition on Gfx12+ 
While this register still exists, it's no longer a per-context register.
Instead, on Gfx12+, SAMPLER_MODE exists per dual-subslice and is
accessed as a "multicast" register, where you write control which
version is accessed by the "steering control register".

At any rate, userspace cannot write it any longer, and so there's not
much point to it existing in our genxml (which was missing most of the
fields anyway).

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15628>
 2022-04-11 19:17:07 +00:00
Kenneth Graunke 8092704705 intel/genxml: Add new "Low Quality Filter" field on Gfx12+. 
This allows the sampler to perform faster filtering of 8-bit UNORM
textures by filtering them at a different precision.  The filtering
is intended to still be OpenGL and DirectX spec compliant.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15628>
 2022-04-11 19:17:07 +00:00
Kenneth Graunke 9a70385e2b intel/genxml: Add SAMPLER_STATE::Allow Low Quality LOD Calculation field 
This allows the hardware to perform a faster LOD calculation in many
simple cases.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15628>
 2022-04-11 19:17:07 +00:00
Lionel Landwerlin 88f77aa811 anv: disable preemption on 3DPRIMITIVE on gfx12 
To workaround a push constant corruption issue.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5963
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5662
Cc: mesa-stable
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15753>
 2022-04-06 12:51:15 +00:00
Lionel Landwerlin 2763a8af5a anv/genxml/intel/fs: fix binding shader record entry 
Bit is flipped compared to all the other packets.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 705395344d ("intel/fs: Add support for compiling bindless shaders with resume shaders")
Fixes: c3ac9afca3 ("anv: Create and return ray-tracing pipeline SBT handles")
Acked-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15078>
 2022-02-19 13:50:56 +00:00
Tapani Pälli 442628b702 intel/genxml: add PIPE_CONTROL field for L3 read only cache invalidation 
Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14815>
 2022-02-09 10:05:10 +00:00
Kenneth Graunke d2646e147b intel/genxml: Add missing MI_FLUSH_DW::Flush CCS field 
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14912>
 2022-02-07 09:50:01 -08:00
Emma Anholt dbcdededb2 intel: Add missing dep of gen_*_header.py on utils.py. 
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14725>
 2022-02-02 11:21:57 -08:00
Caio Marcelo de Oliveira Filho b01c73fd0a intel: Add INTEL_URB_DEREF_BLOCK_SIZE_MESH 
And corresponding value in XML.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13662>
 2022-02-02 18:17:57 +00:00
Lionel Landwerlin 665ffd4bf9 anv: Update VK_KHR_fragment_shading_rate for newer HW 
Per primitive & attachment shading rate support added.

v2: Rebase on KHR_dynamic_rendering

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13739>
 2022-02-02 17:09:46 +00:00
Lionel Landwerlin dff08cbf8e isl: add support for coarse pixel control surfaces 
Those surfaces are used as attachment to rendering passes and describe
the rate of coarse pixel shading for the pass.

v2: Move CPB_BIT tile filtering to isl_gfx125_filter_tiling() (Nanley)

v3: Drop unused macro (Nanley)
    s/isl_to_gen/isl_encode/ (Nanley)
    Remove pitch alignment 128B constraint already covered by tiling (Nanley)
    Move some asserts together (Nanley)

v4: Disable miptail for now (Nanley)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13739>
 2022-02-02 17:09:46 +00:00
Lionel Landwerlin 8bdbc93a9d genxml: add new 3DSTATE_PS_EXTRA bit 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13739>
 2022-02-02 17:09:46 +00:00
Lionel Landwerlin ea71fb0b4b genxml: gen12.5 changes for CPS 
v2: Make genxml look more like BSpec (Caio)
    Fixup X_Focal/Y_Focal entries (Caio)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13739>
 2022-02-02 17:09:46 +00:00
Nanley Chery fde43bb194 intel: Rename a RenderCompressionFormat field 
The name of the bit field is CompressionFormat. The format subsections
of the field specify the alternate names of RenderCompressionFormat or
MediaCompressionFormat depending on the compression type.

We're going to start programming this field for media compression, so
we'd like to use either the bit field name or a new
MediaCompressionFormat field. Either option seems fine, so we go with
the first.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14355>
 2022-01-28 00:30:55 +00:00
Jordan Justen 8db5937f94 intel/genxml: Extend length of 3DSTATE_DEPTH_BUFFER for gfx12.5 
The two added dwords are MBZ.

Ref: bspec 46935
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14702>
 2022-01-26 00:22:54 +00:00
Jordan Justen 315d632977 intel/genxml: Extend length of 3DSTATE_WM_HZ_OP for gfx12.5 
The added dword is MBZ.

Ref: bspec 46981
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14702>
 2022-01-26 00:22:54 +00:00
Kenneth Graunke 3e0bffbad3 intel/genxml: Add XY_BLOCK_COPY_BLT Color Depth enum values 
Requested by Jason.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14687>
 2022-01-24 23:27:25 +00:00
Sagar Ghuge c0849a0697 intel/genxml: Add Un-Typed Data-Port Cache Flush field to pipe control 
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14676>
 2022-01-23 23:46:54 -08:00
Sagar Ghuge 08429da731 intel/genxml: Add L1 Cache Control bit field 
Add L1 cache control bit field to RENDER_SURFACE_STATE and
STATE_BASE_ADDRESS instruction.

v1: (Jason)
- Add prefix to bit field
- Don't miss out STATE_BASE_ADDRESS instruction

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14676>
 2022-01-23 23:43:28 -08:00