69b119bc00
lima: ppir: assign actual index to discard block
...
Discard block is always added to the block list after translation from NIR,
so we can just assign it an index that equals to block list size.
Reviewed-by: Erico Nunes <nunes.erico@gmail.com >
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33754 >
2025-03-06 13:25:40 +00:00
2a56afed8d
radv: switch to device address from vk_buffer
...
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com >
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33897 >
2025-03-06 09:46:01 +00:00
c99039e189
vulkan/meta: Use vk_buffer.device_address directly
...
This saves us jumping through an entrypoing just to fetch a uint64_t.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com >
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com >
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33897 >
2025-03-06 09:46:01 +00:00
b808277d09
hk: Use the new buffer device address infrastructure
...
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33897 >
2025-03-06 09:46:01 +00:00
8ca0531485
panvk: Use the new buffer device address infrastructure
...
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com >
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33897 >
2025-03-06 09:46:00 +00:00
7900ff5c56
nvk: Use the new buffer device address infrastructure
...
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33897 >
2025-03-06 09:46:00 +00:00
73da18b956
vulkan: Add device address helpers to vk_buffer
...
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com >
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com >
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33897 >
2025-03-06 09:46:00 +00:00
c44243099f
ir3: lower immediates to const regs in preamble on a7xx
...
On a7xx, const registers should be loaded via the preamble instead of
uploaded by the driver to the const state. This commit implements this
by adding a new pass that emits the consts created by ir3_cp to a
sequence of stc instructions in the preamble.
Signed-off-by: Job Noorman <jnoorman@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32454 >
2025-03-06 08:47:54 +00:00
fbe8fc0dae
ir3: fix max const size calculation for the binning pass
...
The binning pass should never exceed the const size of the non-binning
pass.
Signed-off-by: Job Noorman <jnoorman@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32454 >
2025-03-06 08:47:54 +00:00
434b82469f
ir3: make const_imm_index_to_reg helper public
...
Signed-off-by: Job Noorman <jnoorman@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32454 >
2025-03-06 08:47:54 +00:00
68ab25e6d4
ir3: split immediate state from rest of const state
...
On a7xx, the immediates that get promoted to const registers will be
initialized in the preamble instead of being part of the const state. So
technically, we won't need the immediate state that is part of the const
state anymore on a7xx. However, it is still a convenient place for
ir3_cp to store the immediates that should be promoted to const
registers before they are lowered to the preamble.
This causes one issue: the binning pass isn't allowed to modify the
const state while it's perfectly fine for it to use different immediates
compared to the non-binning pass on a7xx. Even pre-a7xx this is fine as
long as the size of the immediate buffer is the same.
To allow the binning pass to modify its immediate state while keeping
its const state immutable, this commit moves the fields related to
immediates into a new struct. Runtime checks are added to enforce that
the size of the immediate buffer is the same for the binning and
non-binning variant pre-a7xx.
Signed-off-by: Job Noorman <jnoorman@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32454 >
2025-03-06 08:47:54 +00:00
f9fc0fc8fd
ir3/sched: handle dependencies between stc and const reads
...
Signed-off-by: Job Noorman <jnoorman@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32454 >
2025-03-06 08:47:54 +00:00
0f6ec14925
ir3: fix false dependencies of rpt instructions
...
When merging multiple instructions into one rpt instruction, the false
deps of the rpt instruction should be the union of the false deps of its
parts.
Signed-off-by: Job Noorman <jnoorman@igalia.com >
Fixes: 4c4366179bhttps://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32454 >
2025-03-06 08:47:54 +00:00
62d2069617
ir3: add helper to create STC
...
Creating STC is complicated since we might need to use a1.x for
addressing. Extract the current code into a helper so that it can be
used elsewhere.
Signed-off-by: Job Noorman <jnoorman@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32454 >
2025-03-06 08:47:53 +00:00
3186443057
ir3: remove hash table for a1.x
...
Removing duplicates is now supported by ir3_cse so the hash table is
unnecessary. Removing it will make it easier to create instructions
using a1.x without having access to ir3_context.
Signed-off-by: Job Noorman <jnoorman@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32454 >
2025-03-06 08:47:53 +00:00
06978e0c0c
ir3/cse: add support for mov a0.x/a1.x
...
Signed-off-by: Job Noorman <jnoorman@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32454 >
2025-03-06 08:47:53 +00:00
ac18eccd74
ir3: add ir3_cursor_current_block helper
...
Signed-off-by: Job Noorman <jnoorman@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32454 >
2025-03-06 08:47:53 +00:00
69982e6f2f
nak: Flatten AttrAccess into instructions
...
The AttrAccess structure provided inputs for similar instructions, some
inputs were used only in a subset of instructions, needing asserts and
dummy values.
This commit flattens the struct directly in the instructions removing
the unused fields and cleaning up the code.
Signed-off-by: Lorenzo Rossi <snowycoder@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33899 >
2025-03-06 05:29:56 +00:00
2c034470ed
docs: add sha sum for 25.0.1
...
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33904 >
2025-03-06 04:07:22 +00:00
4fb7c57e29
docs: add release notes for 25.0.1
...
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33904 >
2025-03-06 04:07:22 +00:00
487af01696
docs: update calendar for 25.0.1
...
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33904 >
2025-03-06 04:07:20 +00:00
24dbc278f0
tnn: nir: Don't use deprecated NIR_PASS_V macro anymore
...
Signed-off-by: Corentin Noël <corentin.noel@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33686 >
2025-03-06 03:29:21 +00:00
acd5f2971a
ntt: nir: Don't use deprecated NIR_PASS_V macro anymore
...
Signed-off-by: Corentin Noël <corentin.noel@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33686 >
2025-03-06 03:29:20 +00:00
eb1274ef08
nir: Add bool return value to nir_legacy_trivialize(..)
...
Signed-off-by: Corentin Noël <corentin.noel@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33686 >
2025-03-06 03:29:20 +00:00
8eae89f3f0
virgl: nir: Don't use deprecated NIR_PASS_V macro anymore
...
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33686 >
2025-03-06 03:29:20 +00:00
71e2ddcede
etnaviv/ci: Add gles2 run for GC3000
...
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33838 >
2025-03-06 03:09:12 +00:00
9a88afecbd
amd/vpelib: More parameters to the segmentation process and introduce validation hook
...
Generalization for the following:
1. pass in the scaler output alignment requirement to segment number determination function
2. parameter validation hook
Signed-off-by: Navid Assadian <Navid.Assadian@amd.com >
Reviewed-by: Roy Chan <Roy.Chan@amd.com >
Reviewed-by: Jesse Agate <Jesse.Agate@amd.com >
Acked-by: Alan Liu <Haoping.Liu@amd.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33833 >
2025-03-06 02:11:53 +00:00
37c244998a
amd/vpelib: Fix studio output CSC
...
Fix studio output CSC.
Signed-off-by: Jiali Zhao <Jiali.Zhao@amd.com >
Reviewed-by: Roy Chan <Roy.Chan@amd.com >
Reviewed-by: Evan Damphousse <Evan.Damphousse@amd.com >
Acked-by: Alan Liu <Haoping.Liu@amd.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33833 >
2025-03-06 02:11:53 +00:00
da04cbca66
amd/vpelib: Apply normalization for full range
...
[WHY]
The full range needs to have the same brightness normalization like the
studio range.
[HOW]
Apply the same normalization.
Signed-off-by: Tiberiu Visan <Tiberiu.Visan@amd.com >
Reviewed-by: Tomson Chang <Tomson.Chang@amd.com >
Reviewed-by: Jesse Agate <Jesse.Agate@amd.com >
Acked-by: Alan Liu <Haoping.Liu@amd.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33833 >
2025-03-06 02:11:53 +00:00
b3d43cea08
amd/vpelib: Fix studio range
...
[WHY]
Studio signal has an offset.
[HOW]
Subtract that offset.
Signed-off-by: Tiberiu Visan <Tiberiu.Visan@amd.com >
Reviewed-by: Roy Chan <Roy.Chan@amd.com >
Reviewed-by: Navid Assadian <Navid.Assadian@amd.com >
Acked-by: Alan Liu <Haoping.Liu@amd.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33833 >
2025-03-06 02:11:53 +00:00
69c331e2c0
amd/vpelib: Reformat index variables and update enum
...
Reformat index variables to indicate loop specifics and update enum to match formatting guide.
Signed-off-by: Brendan Steve Leder <Brendansteve.Leder@amd.com >
Reviewed-by: Roy Chan <Roy.Chan@amd.com >
Reviewed-by: Evan Damphousse <Evan.Damphousse@amd.com >
Acked-by: Alan Liu <Haoping.Liu@amd.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33833 >
2025-03-06 02:11:53 +00:00
6528ee4228
lima: ppir: reuse load_temp/store_temp nodes if possible
...
Currently spilling code operates on individual ops rather than on
instructions, and as a result it may create a redundant load_temp op if
an instruction references spilling register several times.
Similarly, it creates multiple stores if there are multiple ops in the
instruction that write different components of the register.
Check whether the instruction already contains a necessary load_temp or
store_temp and reuse it if possible.
shader-db:
total instructions in shared programs: 27718 -> 27673 (-0.16%)
instructions in affected programs: 2786 -> 2741 (-1.62%)
helped: 18
HURT: 0
helped stats (abs) min: 1 max: 8 x̄: 2.50 x̃: 1
helped stats (rel) min: 0.39% max: 5.33% x̄: 2.05% x̃: 0.80%
95% mean confidence interval for instructions value: -3.70 -1.30
95% mean confidence interval for instructions %-change: -3.09% -1.01%
Instructions are helped.
total loops in shared programs: 4 -> 4 (0.00%)
loops in affected programs: 0 -> 0
helped: 0
HURT: 0
total spills in shared programs: 390 -> 381 (-2.31%)
spills in affected programs: 145 -> 136 (-6.21%)
helped: 9
HURT: 0
total fills in shared programs: 1210 -> 1174 (-2.98%)
fills in affected programs: 149 -> 113 (-24.16%)
helped: 9
HURT: 0
LOST: 0
GAINED: 0
Reviewed-by: Erico Nunes <nunes.erico@gmail.com >
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33753 >
2025-03-06 01:48:55 +00:00
7200cf8827
radv: don't unnecessarily flag prolog recalc when binding VBOs
...
another 25% for vkoverhead@draw_vbo_change_dynamic
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33806 >
2025-03-06 01:26:02 +00:00
4f71370830
radv: get vbo info directly into dgc upload
...
don't need this memcpy
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33806 >
2025-03-06 01:26:02 +00:00
b78835de13
radv: move non_trivial_format calc to dynamic VI bind
...
this otherwise gets pointlessly recalculated on every draw when a VBO changes
another 10% for vkoverhead@draw_vbo_change_dynamic
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33806 >
2025-03-06 01:26:02 +00:00
42db08c275
radv: split out dynamic vertex input descriptor writing
...
~25% boost to vkoverhead@draw_vbo_change_dynamic
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33806 >
2025-03-06 01:26:02 +00:00
22434edefc
radv: inline some vertex descriptor functions
...
+5-7% in vkoverhead 16
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33806 >
2025-03-06 01:26:02 +00:00
00f51f7215
radv: eliminate a memset in radv_get_vbo_info()
...
very minor perf cost
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33806 >
2025-03-06 01:26:02 +00:00
e2ccd638a8
radv: roll line topology dynamic state changes into existing rast samples flag
...
this eliminates uploading rast samples whenever prim type changes even
when rast samples will not be changed
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33806 >
2025-03-06 01:26:02 +00:00
b2123314bd
radv: store vertex prolog simple input check to cmdbuf on vs bind
...
no need to check this again and again
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33806 >
2025-03-06 01:26:02 +00:00
881d94a40a
radv: store num_attributes to shader info
...
this eliminates a util_last_bit from the prolog hotpath
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33806 >
2025-03-06 01:26:02 +00:00
d40dd4bfb7
radv: rewrite radv_get_line_mode() conditional
...
this was weirdly hard to parse
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33806 >
2025-03-06 01:26:02 +00:00
6c24ac7d21
panfrost: clean up CL meson rules
...
we shouldn't need any of this anymore. I cleared out similar gunk from Asahi, we do the same for Panfrost here.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33879 >
2025-03-06 00:43:59 +00:00
4d6e37066a
meson,clc: set CL standard from meson
...
this is slightly less weird I think.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com >
Reviewed-by: Dylan Baker <dylan.c.baker@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33879 >
2025-03-06 00:43:59 +00:00
c0022b6603
intel: use common CL args
...
this contains two behaviour changes:
* NDEBUG no longer set in debug builds (so asserts work in debug, but are still
stripped out in release as expected).
* macro map set properly for assertions to be reported with proper paths.
together this makes assertions do the right thing on Intel and brings us in
alignment with asahi+panfrost
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33879 >
2025-03-06 00:43:59 +00:00
256cc0c927
meson: set NDEBUG appropriately for OpenCL
...
this strips device-side asserts in release drivers. this is a behaviour change
for asahi/panfrost/nvk, but hopefully a welcome one!
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com >
Reviewed-by: Dylan Baker <dylan.c.baker@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33879 >
2025-03-06 00:43:59 +00:00
f35172b6a4
meson: make CL args common
...
this will let us unify behaviour across drivers a bit more.
no functional change here. (intel is specifically excluded to avoid a functional
change.)
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com >
Reviewed-by: Dylan Baker <dylan.c.baker@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33879 >
2025-03-06 00:43:59 +00:00
54912281a0
brw: Always verify EU compaction in debug mode
...
There's already code to verify that any compacted instruction
that we produce is equivalent to the original uncompacted
instruction -- including detailed output if it fails.
This patch enables this verification in debug build and will
abort in case it fails.
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33821 >
2025-03-06 00:14:14 +00:00
a9592a0c15
panvk: enable subgroupExtendedTypes
...
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33365 >
2025-03-05 22:58:15 +00:00
c4941376a9
pan/bi: lower subgroups before lowering int64
...
nir_lower_int64 doesn't know how to lower 64-bit imul reductions and
scans. Lowering subgroup operations first leaves us with just 64-bit
ballot and read_invocation, which are easily lowered.
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33365 >
2025-03-05 22:58:15 +00:00
Vasily Khoruzhick