Commit Graph

6635 Commits

Author SHA1 Message Date
Emma Anholt f16d3bf042 ir3: Avoid O(n^2) behavior in rpt validation.
We were walking the instructions in the block for each
first-rpt-instruction in the block.  Instead, on the first query per
block, make a set of all the rpts in the block, so we can O(1) check for
the remainder.

shader-db runtime for deadspace3 -7.60909% +/- 2.28996% (n=10) on a
debugoptimized build.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37625>
2025-10-07 18:55:39 +00:00
Dhruv Mark Collins 4e762df664 tu/util: Allow setting all TU_DEBUG options from envvar and file
Due to the division of TU_DEBUG options into runtime and envvar
options, it limited where options could be set from when
TU_DEBUG_FILE was being used. This commit addresses that by allowing
the envvar to set runtime debug options even when TU_DEBUG_FILE is
active while also allowing the file to set non-runtime options if
the file included them at startup.

Signed-off-by: Dhruv Mark Collins <mark@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37580>
2025-10-07 16:13:33 +00:00
Martin Roukala (né Peres) 1514a851c8 turnip/ci: enable a750_vk in marge pipelines
The DUTs have been in use for over 2 weeks and the new jobs landed over
1 week ago, without new unknown problems cropping up (not bullet-proof
ethernet gadget).

Additionally, the high temperature (up to 95°C) was discussed with
@lumag and he is not concerned by it... so let's move the jobs to the
merge pipeline!

Reviewed-by: Eric Engestrom <eric@igalia.com>
Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37612>
2025-10-07 07:44:35 +00:00
Connor Abbott e5353fd917 tu: Reset *_BIN_FOVEAT when not using FDM
Don't let old values from a previous renderpass through.

Fixes: b34b089ca1 ("tu: Use GRAS bin offset registers")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37723>
2025-10-06 22:42:32 +00:00
Juan A. Suarez Romero d775f3b608 ci: uprev VKCTS to 1.4.3.3
Reviewed-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37620>
2025-10-06 21:53:39 +00:00
Rob Clark e60d34fa78 freedreno: Disable explicit sync heuristic for Xwayland
Xwayland seems to mix implicit and explicit sync, depending on client
app.  This trips up the heuristic that disables implicit sync once it
starts seeing app using explicit sync.  This is not typical behavior,
so add a driconf override to disable the heuristic.

Fixes: 137cd3b0fa ("freedreno/drm: Move no_implicit_sync accounting")
Cc: mesa-stable
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37703>
2025-10-06 15:55:48 +00:00
Zan Dobersek 27c16c46fd fd: allow limiting RD dumps to specific frames and submits
RD dump generation can be expensive and can only be desired for some
specific part of execution. Trigger file mechanism helps with this to a
certain degree but is still somewhat inexact.

FD_RD_DUMP_SUBMITS environment variable can be used to specify ranges of
submit indices for which RD dumps of command streams should be generated.
FD_RD_DUMP_FRAMES environment variable can similarly be used to specify
ranges of frames under which RD dumps for submitted command streams should
be generated. Frame ranges only really work with Turnip since the frame
count data is available there.

Signed-off-by: Zan Dobersek <zdobersek@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37499>
2025-10-06 12:07:55 +00:00
Timothy Arceri 2f799ef0f1 Reapply "ci/freedreno: Skip overly-slow trace"
This reverts commit e2217192fa.

Unfortunately this is still timing out.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37709>
2025-10-05 17:50:06 +11:00
Timothy Arceri e2217192fa Revert "ci/freedreno: Skip overly-slow trace"
This reverts commit 1754bfa94a.

The timeout issue should be solve by the previous commit.

Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37386>
2025-10-05 05:29:36 +00:00
Rob Clark ffcb8d0b89 freedreno/fdl: Set pitch for buffers
In the import path, we test pitch.  So if we are to be able to import
buffers, we should also set the pitch for buffers.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37696>
2025-10-03 23:44:39 +00:00
Rob Clark 7034e65bba freedreno/decode/scripts: Add license comments
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37689>
2025-10-03 16:35:05 +00:00
Danylo Piliaiev 24235bcac3 tu/perfetto: Use a separate track for VK_EXT_debug_utils labels
Labels set via VK_EXT_debug_utils are in a separate track due to the
following part of the spec:
 "An application may open a debug label region in one command buffer and
  close it in another, or otherwise split debug label regions across
  multiple command buffers or multiple queue submissions."

This means labels can start in one renderpass and end in another command
buffer, which breaks our assumption that stages can be modeled as a stack.
While applications aren't expected to use labels in such extreme ways,
even simpler cases can break our assumptions.

Having annotations in a separate track prevents the main track(s) from
entering an invalid state.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37028>
2025-09-26 15:45:21 +00:00
Simon McVittie 9d36bf891b vulkan: Compute path to write into JSON manifests once, use it everywhere
This reduces duplication: we only need to distinguish between Windows
and Unix in one place.

The previous code was inconsistent about using either the `platforms`
option, or the `host_machine`. Following the logic described in
commit 94379377 "lavapipe: build "Windows" check should use the host machine, not the `platforms` option.",
I've assumed that checking the host machine is the more-correct version
and used that.

Signed-off-by: Simon McVittie <smcv@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37576>
2025-09-26 10:47:31 +00:00
Simon McVittie be8cac52d3 vulkan: Consistently form driver library names as prefix + name + suffix
This consistently uses `NAME.dll` on Windows, `libNAME.dylib` on Darwin
derivatives such as macOS, and `libNAME.so` on Linux, *BSD and so on.
It's also consistent about using the local variable name `icd_file_name`
for this name in every Vulkan driver, which was already the case in many
but not all drivers.

Some of these drivers probably don't make sense (or don't work) on
Windows and/or macOS, but if this is kept consistent for all drivers,
it should avoid the need for driver-specific commits like
commit 611e9f29e "lavapipe: fix icd generation for windows",
commit 951f3287 "lavapipe: set empty dll prefix",
commit 13e7a39f "lavapipe: fixes for macOS support",
commit 7008e655 "radv: Update JSON generator if Windows" and so on,
each time a driver is found to be relevant on more platforms than
previously believed.

Signed-off-by: Simon McVittie <smcv@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37576>
2025-09-26 10:47:31 +00:00
Job Noorman 30703e1d7d freedreno/computerator: disable disk cache
Fixes a crash during startup because `build_id_find_nhdr_for_addr`
returns null. Besides that, using the compiler cache is meaningless for
computerator.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37572>
2025-09-25 16:01:04 +00:00
Zan Dobersek 45dcbcfc02 tu: limit query pool types logged into RMV
RMV only supports logging three types of query pools as created resources.
Filtering unsupported ones will avoid asserts when these tokens are
processed during RMV trace output.

Signed-off-by: Zan Dobersek <zdobersek@igalia.com>
Reviewed-by: Karmjit Mahil <karmjit.mahil@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37560>
2025-09-25 11:00:20 +00:00
Connor Abbott c2eb768eb2 tu: Expose VK_EXT_dynamic_rendering_unused_attachments
We only use attachment formats for things used by the pipeline, so we
can trivially enable this.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37529>
2025-09-23 17:33:19 +00:00
Danylo Piliaiev fce9dbc493 tu/perfetto: Init perfetto datasources once
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37465>
2025-09-23 12:04:01 +00:00
Danylo Piliaiev 0621d5cd39 tu/perfetto: Make GPU clock sequence-scoped
When CPU clock is the same with the authoritative trace clock (normally
default to CLOCK_BOOTTIME), perfetto drops the non-monotonic snapshots
to ensure validity of the global source clock in the resolution graph.
When they are different, the clocks are marked invalid and the rest of
the clock syncs will fail during trace processing.

There's no central daemon emitting consistent snapshots for
synchronization between CPU and GPU clocks on behalf of renderstages and
counters producers. The sequence-scoped clock (64 <= ID < 128) is unique
per producer + writer pair within the tracing session.

Turnip is a bit tricky here, since clocks may be synchronized before
`tu_perfetto_end_submit` is called (in case of KGSL), but emission of
perfetto event has to happen on the same thread as other renderstage events.
To solve this I save the clocks in `tu_perfetto_state` and emit them in
`stage_end` when needed.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37465>
2025-09-23 12:04:01 +00:00
Danylo Piliaiev 09f5c9d0ad tu/perfetto: Track GPU timestamps per-device
In preparation for using sequence-scope perfetto clocks.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37465>
2025-09-23 12:04:01 +00:00
Danylo Piliaiev e2b63472e4 tu/perfetto: Don't check sync_gpu_ts when emitting renderstage
In short, perfetto doesn't require the initial clock snapshot to be
earlier than the timestamp to be converted. So we don't have to do
complex handling for it.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37465>
2025-09-23 12:04:01 +00:00
Danylo Piliaiev ea849b5557 tu: Destroy all mutexes used for device
We never destroyed most of mutexes we used, it was likely fine on
platforms turnip is running on, but still not correct.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37465>
2025-09-23 12:04:00 +00:00
Job Noorman f536d76341 ir3/parser: don't use instr as ralloc context
Instructions are allocated using a linear context so cannot themselves
be used as a ralloc context anymore. Use the variant's ir instead.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Fixes: 114e6a3104 ("ir3: Use a linear allocation context for ir3_instructions.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37523>
2025-09-23 11:45:07 +00:00
Danylo Piliaiev 518008c3b0 tu/a7xx: Update reg stomping info to fix GPU crashes when stomping
- Removed DBG/CHICKEN regs from being stomped, because they randomly
  cause issues, and there is no even point of stomping them.
- *ATTR_BUF_GMEM regs are not emitted at every renderpass.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37372>
2025-09-23 10:12:30 +00:00
Connor Abbott a7922e7188 tu/fdm: Use better bounds for LRZ overallocation with FDM offset
Use tile_max_w/h which is the HW bound for the tile width/height and is
much smaller than the theoretical maximum width/height with a lopsided
tile with just the depth attachment.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37513>
2025-09-22 17:01:05 +00:00
Connor Abbott 964e84d468 tu: Fix 3d load and clear when FDM bin offsets are in use
Unlike the store/resolve that uses A2D, The FDM load path uses the 3d
pipeline and is therefore affected by the hardware FDM offset registers.
The fallback sysmem clear path also uses the 3d pipeline. Subtract off
the HW offset from the destination coordinates, similar to how it is
subtracted from viewport and scissor.

Fixes: b34b089ca1 ("tu: Use GRAS bin offset registers")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37496>
2025-09-22 15:17:39 +00:00
Zan Dobersek d3cedd2fa5 tu/drm: msm's has_set_iova codepath should avoid freeing zombified tu_sparse_vma
In msm backend's has_set_iova codepath, mapping a BO into a lazy VMA will
require moving that VMA into the zombie VMA mechanism once the BO is
destroyed. That means tu_sparse_vma destruction should avoid freeing VMA if
BO was mapped into it and then zombified.

Signed-off-by: Zan Dobersek <zdobersek@igalia.com>
Fixes: 764b3d9161 ("tu: Implement transient attachments and lazily allocated memory")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37413>
2025-09-22 13:05:34 +00:00
Zan Dobersek 64fc91bb58 tu/drm: msm backend shouldn't use util_vma_heap in the !has_set_iova codepaths
For the fallback !has_set_iova codepath, util_vma_heap shouldn't be used
for freeing allocations since it's not initialized or used for allocations.

A helper tu_free_iova() function is added to complement tu_allocate_iova(),
handling the vma lock and freeing the allocation in the util_vma_heap when
appropriate.

Signed-off-by: Zan Dobersek <zdobersek@igalia.com>
Fixes: 93a80f4bb9 ("tu/drm: Split out iova allocation and BO allocation")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37413>
2025-09-22 13:05:34 +00:00
Zan Dobersek 07a599ff3e tu/drm: avoid has_set_iova-specific util_vma_heap freeing in tu_bo_init
After the refactoring, tu_bo_init() is not allocating iova anymore so it
should also not free the util_vma_heap allocation for the has_set_iova
case.

Signed-off-by: Zan Dobersek <zdobersek@igalia.com>
Fixes: 93a80f4bb9 ("tu/drm: Split out iova allocation and BO allocation")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37413>
2025-09-22 13:05:33 +00:00
Rob Clark 3a4b3322d4 freedreno/decode: checkreg handling for bitsize/stride
The initial version was not accounting for reg64 vs reg32, or array
stride.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37502>
2025-09-21 08:27:00 -07:00
Rob Clark 159d0596c4 freedreno/registers: Fix x_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE
The HLSQ version only existed in a6xx.  And the SP one had the wrong
offset.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37484>
2025-09-20 16:52:22 +00:00
Rob Clark 897a47602a freedreno/registers: Remove conflicting RBBM regs
These are the same as a6xx, so just keep the declarations without
variants attribute.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37484>
2025-09-20 16:52:21 +00:00
Rob Clark 68e5f150e3 freedreno/decode: Add test to check for conflicting regs
Add a tool to check for conflicting/overlapping register definitions.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37484>
2025-09-20 16:52:21 +00:00
Karmjit Mahil 2c676a38ea freedreno/registers: Fix typo
Signed-off-by: Karmjit Mahil <karmjit.mahil@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37489>
2025-09-19 20:19:41 +00:00
Mike Blumenkrantz 4b30df4462 tu: don't deref end info in tu_CmdEndRendering2EXT
this can be null

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37476>
2025-09-19 10:13:58 -04:00
Martin Roukala (né Peres) e4668b8427 turnip/ci: switch vkcts testing to the KWS farm
This commit keeps vkcts as a nightly job, but this puts us in shooting
distance to what we've been working for for the past 2.5 years!

We will flip the switch to making this job part of the merge pipeline
after a week of stress testing to make sure reliability issues,
especially around USB, don't come back to haunt my days and nights.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37367>
2025-09-19 11:41:54 +00:00
Martin Roukala (né Peres) e5509237bf turnip/ci: document more flakes
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37367>
2025-09-19 11:41:54 +00:00
Danylo Piliaiev 0908694f02 freedreno/decode: Fix preamble decoding
Fixes: 46ad5a01a8 ("freedreno: Rename CP_SET_CTXSWITCH_IB to CP_SET_AMBLE")

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37458>
2025-09-18 14:44:33 +00:00
Emma Anholt 114e6a3104 ir3: Use a linear allocation context for ir3_instructions.
Again, instrs don't get freed as we go, so the linear gc context saves us
5 pointers per instr.

Fossil replay time for deadspace3 on a debugoptimized build -4.85258% +/-
3.04009% (n=10)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37316>
2025-09-17 12:02:47 -07:00
Emma Anholt 12fae29ec2 ir3: Use a linear allocation context for ir3_registers.
Since we don't free registers as we go, we can just allocate them in a
linear gc context that gets freed at ralloc destroy.  Saves 5 pointers of
memory per register for the ralloc overhead.

Fossil replay time for deadspace3 on a debugoptimized build -4.30353% +/-
1.80078% (n=10).

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37316>
2025-09-17 12:02:47 -07:00
Emma Anholt 1b4c2c1566 ir3: Use a bitset for the defs-seen table.
Fossil reply time for deadspace3 on a debugoptimized build -3.20856% +/-
1.48994% (n=15).

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37316>
2025-09-17 12:02:47 -07:00
Karmjit Mahil 9c6183604f nir, ir3: Add lower_fmulz_with_abs_min backend option
This commits adds the `lower_fmulz_with_abs_min` which lowers
`fmulz` -> `min(abs(a), abs(b)) == 0.0 ? 0.0 : a * b`
`ffmaz` -> `min(abs(a), abs(b)) == 0.0 ? c : ffma(a, b, c)

This is useful for ISAs which have `abs` for free on `min` such as
ir3.

Adreno A750 Benchmark of 10 runs of 5 DX9 single frame trimmed
captures looped 2048 times using u_trace measuring
`start_render_pass` to `end_render_pass` results:

sysmem:
-1.91156%, -2.21791%, -2.02533%, -2.21666%, -2.33272%,
-2.67349%, -1.75278%, -2.05923%, -2.26892%, -2.10506%
Avg:  ~ -2.16%
ST.S: ~  0.25%

gmem:
-3.61496%, -3.66682%, -3.80901%, -3.51198%, -3.72950%,
-3.71413%, -3.64467%, -3.67092%, -3.90640%, -3.83888%
Avg:  ~ -3.71%
ST.S: ~  0.12%

Signed-off-by: Karmjit Mahil <karmjit.mahil@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31479>
2025-09-17 15:02:50 +00:00
Konstantin Seurer ea51a67996 vulkan/bvh: Enable glsl extensions in meson
Having a list of all enabled/used extensions in meson allows us to get
rid of a lot of boilerplate in every bvh build shader.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35326>
2025-09-16 20:18:01 +00:00
Rob Clark 0a1f56fb90 freedreno/devices: Update chicken bits
b22 should be set on all a7xx.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37411>
2025-09-16 16:21:42 +00:00
Danylo Piliaiev 1c57f88908 tu: Reset BIN_FOVEAT regs for tiling with and without HW binning
We didn't reset the regs when HW binning was disabled.

Fixes: b34b089ca1 ("tu: Use GRAS bin offset registers")

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37373>
2025-09-15 20:11:21 +00:00
Job Noorman 563b0b347a ir3: don't create merge sets for subreg moves
There are multiple places where RA assumes merge sets are either
all-full or all-half registers. Creating merge sets for subreg moves
mixes full and half registers which may lead to RA failures.

Fix this by not creating merge sets for subreg moves anymore. Instead,
we manually try to allocate  a subreg move's src for its dst when
selecting a register during RA, similar to how ALU/SFU instructions try
to reuse their srcs.

Totals:
Instrs: 363174291 -> 363175216 (+0.00%); split: -0.00%, +0.00%
CodeSize: 922975364 -> 922977230 (+0.00%); split: -0.00%, +0.00%
NOPs: 47652421 -> 47652444 (+0.00%); split: -0.00%, +0.00%
MOVs: 15652959 -> 15653065 (+0.00%); split: -0.00%, +0.00%
COVs: 4097203 -> 4097052 (-0.00%); split: -0.01%, +0.00%
(ss): 7806025 -> 7806183 (+0.00%); split: -0.00%, +0.00%
(sy): 3981862 -> 3981855 (-0.00%); split: -0.00%, +0.00%
(ss)-stall: 26612057 -> 26612789 (+0.00%); split: -0.00%, +0.00%
(sy)-stall: 111568786 -> 111568721 (-0.00%); split: -0.00%, +0.00%
STPs: 345796 -> 345792 (-0.00%)
LDPs: 191118 -> 191111 (-0.00%)
Preamble Instrs: 160491915 -> 160492355 (+0.00%); split: -0.00%, +0.00%
Last helper: 116587870 -> 116588273 (+0.00%); split: -0.00%, +0.00%
Cat0: 53288367 -> 53288384 (+0.00%); split: -0.00%, +0.00%
Cat1: 20954383 -> 20954336 (-0.00%); split: -0.00%, +0.00%
Cat2: 155294307 -> 155295252 (+0.00%); split: -0.00%, +0.00%
Cat6: 4623070 -> 4623059 (-0.00%)
Cat7: 9302363 -> 9302384 (+0.00%); split: -0.00%, +0.00%

Totals from 979 (0.07% of 1352016) affected shaders:
Instrs: 1324850 -> 1325775 (+0.07%); split: -0.07%, +0.14%
CodeSize: 2596114 -> 2597980 (+0.07%); split: -0.04%, +0.11%
NOPs: 330197 -> 330220 (+0.01%); split: -0.23%, +0.24%
MOVs: 62592 -> 62698 (+0.17%); split: -0.35%, +0.52%
COVs: 49011 -> 48860 (-0.31%); split: -0.62%, +0.31%
(ss): 35671 -> 35829 (+0.44%); split: -0.28%, +0.73%
(sy): 18936 -> 18929 (-0.04%); split: -0.13%, +0.09%
(ss)-stall: 157929 -> 158661 (+0.46%); split: -0.36%, +0.82%
(sy)-stall: 543371 -> 543306 (-0.01%); split: -0.20%, +0.19%
STPs: 2741 -> 2737 (-0.15%)
LDPs: 3022 -> 3015 (-0.23%)
Preamble Instrs: 322588 -> 323028 (+0.14%); split: -0.01%, +0.14%
Last helper: 298996 -> 299399 (+0.13%); split: -0.05%, +0.19%
Cat0: 361575 -> 361592 (+0.00%); split: -0.21%, +0.22%
Cat1: 111733 -> 111686 (-0.04%); split: -0.45%, +0.41%
Cat2: 487366 -> 488311 (+0.19%); split: -0.04%, +0.23%
Cat6: 21239 -> 21228 (-0.05%)
Cat7: 37170 -> 37191 (+0.06%); split: -0.06%, +0.12%

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Fixes: c757b22c5f ("ir3: add subreg move optimization")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37368>
2025-09-15 15:07:47 +00:00
Daniel Stone 1754bfa94a ci/freedreno: Skip overly-slow trace
The Godot trace has started timing out, taking close to or over 5min to
run. It's been skipped out on zink-tu-a618 for this reason, so do it on
the native driver too.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13894
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37366>
2025-09-15 10:03:22 +00:00
Yonggang Luo bebd167d74 glsl: Fixes warning: deprecated directive: ‘%pure-parser’, ‘%error-verbose’
../../src/compiler/glsl/glcpp/glcpp-parse.y:179.1-12: warning: deprecated directive: ‘%pure-parser’, use ‘%define api.pure’ [-Wdeprecated]
  179 | %pure-parser
      | ^~~~~~~~~~~~
      | %define api.pure
../../src/compiler/glsl/glcpp/glcpp-parse.y:180.1-14: warning: deprecated directive: ‘%error-verbose’, use ‘%define parse.error verbose’ [-Wdeprecated]
  180 | %error-verbose
      | ^~~~~~~~~~~~~~
      | %define parse.error verbose

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37289>
2025-09-13 08:23:07 +00:00
Collabora's Gfx CI Team db3501ec4f Uprev Piglit to 517270ccca11a795d2f29bd723c362eb6ef9ce8f
https://gitlab.freedesktop.org/mesa/piglit/-/compare/28d1349844eacda869f0f82f551bcd4ac0c4edfe...517270ccca11a795d2f29bd723c362eb6ef9ce8f

Signed-off-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37273>
2025-09-12 23:09:46 -03:00
Eric Engestrom 11a7693065 turnip/ci: update test expectations
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37302>
2025-09-11 16:02:38 +00:00