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freedreno/registers: Fix x_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE

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The HLSQ version only existed in a6xx.  And the SP one had the wrong
offset.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37484>
This commit is contained in:
Rob Clark
2025-09-19 10:39:29 -07:00
committed by Marge Bot
parent 897a47602a
commit 159d0596c4
4 changed files with 8 additions and 8 deletions
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src/freedreno/registers/adreno/a6xx.xml
+2 -2
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@@ -3276,7 +3276,7 @@ by a particular renderpass/blit.
<array offset="0xae80" name="SP_PERFCTR_SP_SEL" stride="1" length="36" variants="A7XX-"/>
<!-- TODO: there are 4 more percntr select registers (0xae28-0xae2b) -->
<!-- TODO: there are a few unknown registers in the 0xae30-0xae52 range -->
<reg32 offset="0xbe22" name="SP_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE"/>
<reg32 offset="0xae52" name="SP_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE"/>
<!--
The downstream kernel calls the debug cluster of registers
@@ -3788,7 +3788,7 @@ by a particular renderpass/blit.
<array offset="0xbe10" name="HLSQ_PERFCTR_HLSQ_SEL" stride="1" length="6"/>
<!-- TODO: some valid registers between 0xbe20 and 0xbe33 -->
<reg32 offset="0xbe22" name="HLSQ_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE"/>
<reg32 offset="0xbe22" name="HLSQ_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE" variants="A6XX"/>
<reg32 offset="0xc000" name="SP_AHB_READ_APERTURE" variants="A7XX-"/>
src/freedreno/tests/reference/crash.log
+2 -2
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@@ -1587,7 +1587,7 @@ registers:
00000000 HLSQ_PERFCTR_HLSQ_SEL[0x5]+0: 00000000
00000000 0xbe20: 00000000
00000000 0xbe21: 00000000
00000000 SP_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE: 0
00000000 HLSQ_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE: 0
00000000 0xbe23: 00000000
00000000 SP_DBG_ECO_CNTL: 0
00000001 SP_ADDR_MODE_CNTL: ADDR_64B
@@ -1636,7 +1636,7 @@ registers:
deadbeef 0xae3f: deadbeef
deadbeef 0xae50: deadbeef
deadbeef 0xae51: deadbeef
deadbeef 0xae52: deadbeef
deadbeef SP_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE: 0xdeadbeef
00000000 TPL1_DBG_ECO_CNTL: 0
00000001 TPL1_ADDR_MODE_CNTL: ADDR_64B
00000004 TPL1_NC_MODE_CNTL: { LOWER_BIT = 2 | UPPER_BIT = 0 }
src/freedreno/tests/reference/crash_prefetch.log
+2 -2
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@@ -1800,7 +1800,7 @@ registers:
00000000 HLSQ_PERFCTR_HLSQ_SEL[0x5]+0: 00000000
00000000 0xbe20: 00000000
00000000 0xbe21: 00000000
00000000 SP_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE: 0
00000000 HLSQ_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE: 0
00000000 0xbe23: 00000000
00108000 SP_DBG_ECO_CNTL: 0x108000
00000001 SP_ADDR_MODE_CNTL: ADDR_64B
@@ -1849,7 +1849,7 @@ registers:
deadbeef 0xae3f: deadbeef
deadbeef 0xae50: deadbeef
deadbeef 0xae51: deadbeef
deadbeef 0xae52: deadbeef
deadbeef SP_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE: 0xdeadbeef
00108000 TPL1_DBG_ECO_CNTL: 0x108000
00000001 TPL1_ADDR_MODE_CNTL: ADDR_64B
00000002 TPL1_NC_MODE_CNTL: { LOWER_BIT = 1 | UPPER_BIT = 0 }
src/freedreno/tests/reference/prefetch-test.log
+2 -2
View File
@@ -2379,7 +2379,7 @@ registers:
00000000 HLSQ_PERFCTR_HLSQ_SEL[0x5]+0: 00000000
00000000 0xbe20: 00000000
00000000 0xbe21: 00000000
00000000 SP_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE: 0
00000000 HLSQ_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE: 0
00000000 0xbe23: 00000000
00108000 SP_DBG_ECO_CNTL: 0x108000
00000001 SP_ADDR_MODE_CNTL: ADDR_64B
@@ -2428,7 +2428,7 @@ registers:
deadbeef 0xae3f: deadbeef
deadbeef 0xae50: deadbeef
deadbeef 0xae51: deadbeef
deadbeef 0xae52: deadbeef
deadbeef SP_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE: 0xdeadbeef
00108000 TPL1_DBG_ECO_CNTL: 0x108000
00000001 TPL1_ADDR_MODE_CNTL: ADDR_64B
00000002 TPL1_NC_MODE_CNTL: { LOWER_BIT = 1 | UPPER_BIT = 0 }