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Author SHA1 Message Date
Georg Lehmann 56aac9fdec nir/opt_algebraic: optimize ffract(ffract(a)) 
Foz-DB Navi21:
Totals from 163 (0.21% of 79377) affected shaders:
Instrs: 233933 -> 233685 (-0.11%)
CodeSize: 1252492 -> 1251500 (-0.08%); split: -0.08%, +0.00%
Latency: 1227625 -> 1227405 (-0.02%); split: -0.02%, +0.00%
InvThroughput: 266954 -> 266668 (-0.11%)
VClause: 4193 -> 4191 (-0.05%)
Copies: 20935 -> 20932 (-0.01%); split: -0.02%, +0.01%
PreSGPRs: 10395 -> 10391 (-0.04%)
VALU: 163725 -> 163475 (-0.15%)

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33557>
 2025-02-18 20:38:57 +00:00
Georg Lehmann 317d07484e nir: improve fsqrt range analysis 
Foz-DB Navi21:
Totals from 3 (0.00% of 79377) affected shaders:
MaxWaves: 88 -> 96 (+9.09%)
Instrs: 1058 -> 951 (-10.11%)
CodeSize: 5964 -> 5368 (-9.99%)
VGPRs: 104 -> 96 (-7.69%)
Latency: 15283 -> 14099 (-7.75%); split: -8.37%, +0.62%
InvThroughput: 4951 -> 4238 (-14.40%)
Copies: 81 -> 76 (-6.17%)
PreVGPRs: 93 -> 84 (-9.68%)
VALU: 820 -> 737 (-10.12%)
SALU: 115 -> 91 (-20.87%)

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33557>
 2025-02-18 20:38:57 +00:00
Georg Lehmann 81b4629636 nir: fix frsq range analysis 
Foz-DB Navi21:
Totals from 98 (0.12% of 79377) affected shaders:
Instrs: 157311 -> 157675 (+0.23%); split: -0.03%, +0.26%
CodeSize: 844296 -> 846648 (+0.28%); split: -0.00%, +0.28%
Latency: 1275467 -> 1276259 (+0.06%); split: -0.00%, +0.06%
InvThroughput: 266980 -> 267098 (+0.04%); split: -0.03%, +0.07%
Copies: 11094 -> 11093 (-0.01%)
PreVGPRs: 5945 -> 5977 (+0.54%)
VALU: 110585 -> 110953 (+0.33%); split: -0.04%, +0.38%
SALU: 18481 -> 18476 (-0.03%)

Cc: mesa-stable

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33557>
 2025-02-18 20:38:56 +00:00
Georg Lehmann 25300ac18a nir: fix range analysis for frcp 
Foz-DB Navi21:
Totals from 448 (0.56% of 79377) affected shaders:
Instrs: 669306 -> 669318 (+0.00%); split: -0.00%, +0.00%
CodeSize: 3736580 -> 3738840 (+0.06%); split: -0.00%, +0.06%
Latency: 5860916 -> 5860961 (+0.00%); split: -0.00%, +0.00%
InvThroughput: 1344094 -> 1344135 (+0.00%); split: -0.00%, +0.00%
VClause: 13878 -> 13879 (+0.01%)
Copies: 58538 -> 58532 (-0.01%)
VALU: 479807 -> 479820 (+0.00%); split: -0.00%, +0.00%

Cc: mesa-stable

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33557>
 2025-02-18 20:38:56 +00:00
Georg Lehmann 1f3494b886 nir: range analysis for ffract 
Foz-DB Navi21:
Totals from 75 (0.09% of 79377) affected shaders:
Instrs: 69239 -> 68383 (-1.24%)
CodeSize: 385088 -> 379532 (-1.44%)
Latency: 427188 -> 421729 (-1.28%); split: -1.28%, +0.00%
InvThroughput: 103086 -> 101926 (-1.13%)
VClause: 785 -> 753 (-4.08%)
SClause: 1624 -> 1598 (-1.60%)
Copies: 5679 -> 5671 (-0.14%); split: -0.72%, +0.58%
PreSGPRs: 3961 -> 3937 (-0.61%)
VALU: 51107 -> 50457 (-1.27%)
SALU: 9034 -> 8950 (-0.93%)
VMEM: 1123 -> 1091 (-2.85%)
SMEM: 2862 -> 2830 (-1.12%)

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33557>
 2025-02-18 20:38:56 +00:00
Aaron Ruby 030c8b57b0 gfxstream: Add reference counting for GEM handles in LinuxVirtGpuBlob 
It's entirely possible that the same GEM handle is referenced across
different Vulkan object instances. As per the warnings in xf86drm.h,
the caller is responsible for reference counting.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33451>
 2025-02-18 20:03:28 +00:00
Aaron Ruby a630efb645 gfxstream: Fix precedence and ownership issues on Linux for imported FD 
and the VirtGpuResource

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33451>
 2025-02-18 20:03:27 +00:00
Paulo Zanoni 927d7b322b brw: increase brw_reg::subnr size to 6 bits 
Since Xe2, the registers are bigger and even the instruction
structures got updated to have 6 bits.

The way I detected this issue was when I tried to use
src/intel/executor to add the following instruction:

    add(8)          g6.8<1>UD      g4<8,8,1>UD    0x00000008UD    { align1 WE_all 1Q I@1 };

Executor would read this and end up emitting an add with dst being
g6<1>UD instead of what we wanted. It turns out that inside
brw_gram.y, at dstoperand and dstoperandex we do:

    $$.subnr = $$.subnr * brw_type_size_bytes($4);

which would overflow subnr back to 0.

The overflow doesn't seem to be a problem with code we emit directly
(unlike the code we parse, like above) due to the fact that we seem to
treat Xe2 registers as smaller all the way until we call phys_nr() and
phys_subnr() during code generation. The phys_subnr() function can
generate a value that would overflow reg.subnr, but this value is
never written back to reg.subnr, it's just returned as an unsigned
int.

Fixes: e9f63df2f2 ("intel/dev: Enable LNL PCI IDs without INTEL_FORCE_PROBE")
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33539>
 2025-02-18 19:38:46 +00:00
Lionel Landwerlin cf3a343800 anv: fixup compute walker storage length 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 9aef4ceb13 ("anv: hold a prepacked COMPUTE_WALKER instruction on CS pipelines")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33593>
 2025-02-18 18:34:51 +00:00
Lionel Landwerlin 66bbb79df9 anv/ci/adl: update fail expectation for video 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33593>
 2025-02-18 18:34:51 +00:00
Tapani Pälli 765f3b78d5 anv: apply cache flushes on pipeline select with gfx20 
This fixes rendering artifacts seen with Hogwarts Legacy and Black
Myth Wukong. Assumption is that we can get rid of these flushes once
RESOURCE_BARRIER work lands but until then we need them.

Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12540
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12489
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33397>
 2025-02-18 18:04:45 +00:00
Lionel Landwerlin 252cac1e5c anv: avoid memory type changes with INTEL_DEBUG=noccs 
Otherwise replay of renderdoc captures don't work.

Instead avoid passing the flag down the allocator.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33583>
 2025-02-18 17:35:44 +00:00
Job Noorman 891132c3ec ir3/legalize: use (sy) for ray_intersection WAR hazards 
It seems like (ss) is not enough to resolve WAR hazards for
ray_intersection.

Fixes CTS tests:
- dEQP-VK.ray_query.stress.fragment_shader.aabbs
- dEQP-VK.ray_query.stress.fragment_shader.triangles

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33597>
 2025-02-18 17:13:33 +00:00
Job Noorman 3f0894df8d ir3: don't create SRC2 for isam without .v 
We would create an immed 0 SRC2 for, for example, load_uav. Even though
this src would be dismissed in the final assembly, it would still waste
a register or alias.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33596>
 2025-02-18 16:13:53 +00:00
Connor Abbott f39679199b tu: Fix vertical tile merging check 
The intent here was to check if the tile we're trying to merge
vertically (prev_y_tile) has already been merged horizontally into a
neighboring tile, but I used the slot_mask which also contains the tiles
that have been merged into the prev_y_tile, so the check was too
conservative and would fail even if another tile had been merged into
prev_y_tile. This meant that we would fail to ever create 2x2 regions of
tiles. Fix this by just testing prev_y_tile's bit in the mask.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33534>
 2025-02-18 14:41:56 +00:00
Connor Abbott 928a857496 tu: Make sure tiles being merged are adjacent 
Even though we always try to merge a horizontally or vertically adjacent
tile, when we try to merge a vertically adjacent tile it may not
actually be adjacent because it was merged horizontally and the current
tile wasn't or vice versa. We have to detect this and reject merging it.

Fixes: 3fdaad0948 ("tu: Implement bin merging for fragment density map")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33534>
 2025-02-18 14:41:56 +00:00
Natalie Vock f01623ea75 radv/bvh: Add custom leaf node builder 
This custom builder implements fine-grained instance node bounds
calculation by looking at all AABBs at tree depth 2.

Shaves off 0.3ms in the start scene for Indiana Jones: The Great Circle
on Deck (roughly 29.1ms->28.7ms).

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32797>
 2025-02-18 13:00:53 +00:00
Natalie Vock 90c3450621 radv/bvh: Prefix RADV-specific node functions with radv_ 
Avoids naming conflicts when including both the common leaf shader and
RADV's build_helpers.h.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32797>
 2025-02-18 13:00:53 +00:00
Natalie Vock 444bd02255 radv/bvh: Remove unused build_instance helper 
This is in common code now.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32797>
 2025-02-18 13:00:53 +00:00
Natalie Vock b1f6d3b6b7 radv/bvh, vulkan/bvh: Move AccelerationStructureInstance to vk_build_helpers 
Remove duplications.

Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32797>
 2025-02-18 13:00:52 +00:00
Natalie Vock 28ed283e81 vulkan/bvh: Add optional fine-grained instance node bounds calculation 
This allows drivers to inject custom functions to calculate the bounds
of instance nodes. For example, this can be used to determine instance
bounds by transforming the AABBs of all child nodes at some level in the
BVH. When instance transforms contain rotations of close to 45°, this
can yield a tighter AABB than just taking the instance's top-level AABB
and rotating it.

Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32797>
 2025-02-18 13:00:52 +00:00
Natalie Vock e39994088a vulkan/bvh: Add option to override leaf builder SPIR-Vs 
With this, drivers can compile and use custom leaf builder versions
instead of the generic common shader.

Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32797>
 2025-02-18 13:00:52 +00:00
Natalie Vock 40b0ad0f45 vulkan/bvh: Move leaf builder code to header 
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32797>
 2025-02-18 13:00:52 +00:00
Rhys Perry d2907d271e ac/nir: set higher alignment for some swizzled store_buffer_amd 
No fossil-db changes (navi31, navi21, polaris10).

fossil-db (vega10):
Totals from 37 (0.06% of 62962) affected shaders:
MaxWaves: 189 -> 180 (-4.76%)
Instrs: 45607 -> 45616 (+0.02%); split: -0.16%, +0.18%
CodeSize: 241980 -> 234908 (-2.92%)
VGPRs: 2524 -> 2784 (+10.30%)
Latency: 152476 -> 151948 (-0.35%); split: -0.38%, +0.03%
InvThroughput: 74441 -> 78360 (+5.26%); split: -0.21%, +5.47%
VClause: 902 -> 1044 (+15.74%); split: -1.55%, +17.29%
Copies: 4989 -> 6745 (+35.20%)
PreVGPRs: 2044 -> 2334 (+14.19%)
VALU: 31634 -> 33389 (+5.55%)
SALU: 2601 -> 2602 (+0.04%)
VMEM: 5774 -> 3991 (-30.88%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33531>
 2025-02-18 12:31:19 +00:00
Rhys Perry 8fd862499a ac/nir: don't cross swizzle elements when vectorizing buffer_amd intrinsic 
This can happen for mesh shader outputs.

No fossil-db changes (navi31, navi21, polaris10).

fossil-db (vega10):
Totals from 37 (0.06% of 62962) affected shaders:
MaxWaves: 183 -> 189 (+3.28%)
Instrs: 45037 -> 45607 (+1.27%); split: -0.09%, +1.36%
CodeSize: 231472 -> 241980 (+4.54%)
VGPRs: 2656 -> 2524 (-4.97%)
Latency: 151199 -> 152476 (+0.84%); split: -0.02%, +0.87%
InvThroughput: 75148 -> 74441 (-0.94%); split: -1.44%, +0.50%
VClause: 882 -> 902 (+2.27%); split: -4.31%, +6.58%
Copies: 6465 -> 4989 (-22.83%)
PreVGPRs: 2265 -> 2044 (-9.76%)
VALU: 33109 -> 31634 (-4.45%)
SALU: 2602 -> 2601 (-0.04%)
VMEM: 3711 -> 5774 (+55.59%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Fixes: c3d27906d8 ("radv: vectorize lowered shader IO")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33531>
 2025-02-18 12:31:19 +00:00
David Rosca ebd8893710 radv/video: Move IB header from begin/end to encode_video 
For decode this is also done in decode_video.

This breaks if app doesn't call vkCmdEncodeVideoKHR before end, eg:

  vkCmdBeginVideoCodingKHR
  vkCmdControlVideoCodingKHR
  vkCmdEndVideoCodingKHR

Cc: mesa-stable
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33582>
 2025-02-18 11:12:22 +00:00
David Rosca 77ff18aa3b radv/video: Fix setting balanced preset for HEVC encode with SAO enabled 
FW disables SAO in speed preset, so we need to switch to balanced.

Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12615
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33582>
 2025-02-18 11:12:22 +00:00
Danylo Piliaiev 49191f46e6 tu/a6xx: Emit VSC addresses for each bin to restore after preemption 
KGSL unconditionally supports preemption so we cannot ignore it.

On a6xx, we have to emit VSC addresses per-bin or make the amble include
these registers, because CP_SET_BIN_DATA5_OFFSET will use the
register instead of the pseudo register and its value won't survive
across preemptions. The blob seems to take the second approach and
emits the preamble lazily. We chose the per-bin approach but blob's
should be a better one.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12627

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33580>
 2025-02-18 10:23:09 +00:00
Samuel Pitoiset 9427df23b4 radv: use radv_image::bindings::addr more 
Also remove radv_image::bindings::offset.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33524>
 2025-02-18 09:49:14 +01:00
Samuel Pitoiset 066467cf98 radv: compute radv_image::bindings::addr at bind time 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33524>
 2025-02-18 09:47:24 +01:00
Samuel Pitoiset f234099d6d radv: rename radv_image::bindings::bo_va to addr 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33524>
 2025-02-18 09:47:24 +01:00
Samuel Pitoiset 0f8b3bf489 radv: remove redundant zero initialization when creating images 
The struct is already zero-allocated.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33524>
 2025-02-18 09:47:24 +01:00
Samuel Pitoiset 63b5bce396 radv: stop using image binding offset when exporting BO metadata 
The offset must be zero for dedicated allocations.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33524>
 2025-02-18 09:47:23 +01:00
Samuel Pitoiset 50851f17d1 radv/meta: remove the buffer dependency for image copy operations 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33526>
 2025-02-18 08:40:30 +01:00
Samuel Pitoiset ae5d2bfd36 radv/meta: use radv_copy_memory() instead of radv_copy_buffer() 
To remove the buffer dependency.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33526>
 2025-02-18 08:40:30 +01:00
Samuel Pitoiset 70bd4fe621 radv/meta: pass the buffer addr to SDMA image buffer copy operations 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33526>
 2025-02-18 08:40:30 +01:00
Samuel Pitoiset 6e2da49e92 radv/meta: add BOs to cmdbuf list earlier for image copy operations 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33526>
 2025-02-18 08:40:30 +01:00
Samuel Pitoiset e0070bc68b radv: fix adding the VRS image BO to the cmdbuf list on GFX11 
This might cause random faults.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33584>
 2025-02-18 07:13:07 +00:00
Tapani Pälli d8381415a6 anv: tighten condition for changing barrier layouts 
Assertion (or attempting the layout change) is causing crash when
launching Steel Rats. Tighten the condition for change so that it should
affect only when runtime has made changes.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12602
Fixes: eed788213b ("anv: ensure consistent layout transitions in render passes")
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33523>
 2025-02-18 06:30:14 +00:00
Vasily Khoruzhick b6fba15bd7 lima: ppir: duplicate fneg and fabs if its source is an intrinsic 
fneg and fabs are folded later in ppir, but having them in nir as a
separate instructions prevents duplicate_intrinsics pass from duplicating
load_input and load_uniform. Duplicate fneg and fabs, so subsequent
duplicate_intrinsic pass can duplicate the loads

shader-db:

total instructions in shared programs: 27698 -> 27675 (-0.08%)
instructions in affected programs: 2752 -> 2729 (-0.84%)
helped: 21
HURT: 2
helped stats (abs) min: 1 max: 4 x̄: 1.19 x̃: 1
helped stats (rel) min: 0.38% max: 6.67% x̄: 2.75% x̃: 0.75%
HURT stats (abs)   min: 1 max: 1 x̄: 1.00 x̃: 1
HURT stats (rel)   min: 1.89% max: 1.89% x̄: 1.89% x̃: 1.89%
95% mean confidence interval for instructions value: -1.39 -0.61
95% mean confidence interval for instructions %-change: -3.67% -1.03%
Instructions are helped.

total loops in shared programs: 2 -> 2 (0.00%)
loops in affected programs: 0 -> 0
helped: 0
HURT: 0

total spills in shared programs: 372 -> 368 (-1.08%)
spills in affected programs: 27 -> 23 (-14.81%)
helped: 4
HURT: 0

total fills in shared programs: 1224 -> 1205 (-1.55%)
fills in affected programs: 81 -> 62 (-23.46%)
helped: 4
HURT: 0

LOST:   0
GAINED: 0

Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33569>
 2025-02-18 02:38:26 +00:00
Faith Ekstrand 86e217e7df nvk: Implement descriptorBufferPushDescriptors 
The only thing we really need to do here is to make sure we don't try
to use the EDB path for push descriptors since those aren't really
descriptor buffers.

Backport-to: 25.0
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33589>
 2025-02-17 23:38:17 +00:00
José Roberto de Souza 7d4c91efef intel/dev: Call intel_device_info_update_after_hwconfig() from common code 
Avoid backends duplication.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33585>
 2025-02-17 20:52:31 +00:00
José Roberto de Souza e170252d97 intel/dev: Improve max_cs_threads documentation 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33585>
 2025-02-17 20:52:31 +00:00
Vasily Khoruzhick dde084d688 lima: ppir: use combiner unit for mul 
Combiner unit runs after fmul/smul/fadd/sadd units and it can consume
the results that previous units wrote to the registers. So prefer
placing scalar mul into combiner unit and predecessors (if any)
into other units

shader-db:

total instructions in shared programs: 29072 -> 27698 (-4.73%)
instructions in affected programs: 11237 -> 9863 (-12.23%)
helped: 163
HURT: 0
helped stats (abs) min: 1 max: 42 x̄: 8.43 x̃: 4
helped stats (rel) min: 0.64% max: 30.00% x̄: 13.03% x̃: 11.76%
95% mean confidence interval for instructions value: -9.89 -6.96
95% mean confidence interval for instructions %-change: -14.09% -11.97%
Instructions are helped.

total loops in shared programs: 2 -> 2 (0.00%)
loops in affected programs: 0 -> 0
helped: 0
HURT: 0

total spills in shared programs: 367 -> 372 (1.36%)
spills in affected programs: 16 -> 21 (31.25%)
helped: 1
HURT: 2

total fills in shared programs: 1208 -> 1224 (1.32%)
fills in affected programs: 51 -> 67 (31.37%)
helped: 2
HURT: 2

LOST:   0
GAINED: 0

Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33568>
 2025-02-17 12:25:01 -08:00
Vasily Khoruzhick bc9fca2fb1 lima: ppir: add codegen for mov and mul on combiner unit 
Combiner unit support scalar by vector multiplication and scalar mov.
Implement it for codegen

Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33568>
 2025-02-17 12:25:01 -08:00
Vasily Khoruzhick 5937d12d29 lima: ppir: assert on unexpected pipeline dest for fmul and vmul 
Assert on unexpected pipeline dest for fmul and vmul to catch scheduler
bugs early

Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33540>
 2025-02-17 19:51:30 +00:00
Vasily Khoruzhick c6c37b516d lima: ppir: fix diassembling atan and combiner codegen definition 
Fix multiple issues with atan in disassembler:

- arg1_en field in combiner unit actually seems to be a bit indicating
  that one of sources is vector (e.g. for atan_pt2, or multiplication)
- atan2 has 2 arguments, not one
- properly handle all instruction variants

Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33540>
 2025-02-17 19:51:30 +00:00
Vasily Khoruzhick f90df9a39e lima: ppir: print index of the node that breaks node_to_instr 
Print index of the node that breaks node_to_instr to make debugging
easier

Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33540>
 2025-02-17 19:51:30 +00:00
Vasily Khoruzhick 7621f9beda lima: ppir: fixup src node when replacing src for select and load_reg 
Fixup src node when replacing src for select and load_reg

It doesn't affect compiler functionality, but affects printing ppir
representation.

Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33540>
 2025-02-17 19:51:30 +00:00
Vasily Khoruzhick 2ea27f41e3 lima: ppir: improve readability of ppir represantation dump 
Improve readability of ppir representation dump

- adopt "dest = op src1[, srcN]"
- use symbolic names of pipeline registers
- print destination writemask
- print destination modifier (if any)
- print source(s) swizzle
- print constants
- print load node base index
- print branch condition(s)

With these modifications it's actually possible to follow the program

-------block   0-------
 $0008 = mov ^texture ($0005) // NIR: new
  ($0005) ^texture = ld_tex ^discard ($0006).xyzx, $0004.xxxx // NIR: ssa4
    ($0006) ^discard = ld_coords_reg $0002.xyzx // NIR: new
       $0004.x = ld_var 0 // NIR: ssa6
       $0002.xyz = mov $0001.yzwx // NIR: ssa5
         $0001 = ld_var 0 // NIR: ssa7

Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33540>
 2025-02-17 19:51:30 +00:00