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ac/nir: set higher alignment for some swizzled store_buffer_amd

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No fossil-db changes (navi31, navi21, polaris10).

fossil-db (vega10):
Totals from 37 (0.06% of 62962) affected shaders:
MaxWaves: 189 -> 180 (-4.76%)
Instrs: 45607 -> 45616 (+0.02%); split: -0.16%, +0.18%
CodeSize: 241980 -> 234908 (-2.92%)
VGPRs: 2524 -> 2784 (+10.30%)
Latency: 152476 -> 151948 (-0.35%); split: -0.38%, +0.03%
InvThroughput: 74441 -> 78360 (+5.26%); split: -0.21%, +5.47%
VClause: 902 -> 1044 (+15.74%); split: -1.55%, +17.29%
Copies: 4989 -> 6745 (+35.20%)
PreVGPRs: 2044 -> 2334 (+14.19%)
VALU: 31634 -> 33389 (+5.55%)
SALU: 2601 -> 2602 (+0.04%)
VMEM: 5774 -> 3991 (-30.88%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33531>
This commit is contained in:
Rhys Perry
2025-02-13 15:38:28 +00:00
committed by Marge Bot
parent 8fd862499a
commit d2907d271e
3 changed files with 18 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/amd/common/nir/ac_nir_lower_legacy_gs.c
+10 -1
View File
@@ -113,12 +113,21 @@ lower_legacy_gs_emit_vertex_with_counter(nir_builder *b, nir_intrinsic_instr *in
/* extend 8/16 bit to 32 bit, 64 bit has been lowered */
nir_def *data = nir_u2uN(b, output, 32);
unsigned align_mul = 4;
unsigned align_offset = 0;
if (nir_src_is_const(intrin->src[0])) {
unsigned v_const_offset = base + nir_src_as_uint(intrin->src[0]) * 4;
align_mul = 16;
align_offset = v_const_offset % align_mul;
}
nir_store_buffer_amd(b, data, gsvs_ring, voffset, soffset, nir_imm_int(b, 0),
.access = ACCESS_COHERENT | ACCESS_NON_TEMPORAL |
ACCESS_IS_SWIZZLED_AMD,
.base = base,
/* For ACO to not reorder this store around EmitVertex/EndPrimitve */
.memory_modes = nir_var_shader_out);
.memory_modes = nir_var_shader_out,
.align_mul = align_mul, .align_offset = align_offset);
}
}
src/amd/common/nir/ac_nir_lower_ngg_mesh.c
+4 -2
View File
@@ -330,7 +330,8 @@ ms_store_arrayed_output(nir_builder *b,
.base = const_off + param_offset * 16,
.write_mask = write_mask,
.memory_modes = nir_var_shader_out,
.access = ACCESS_COHERENT | ACCESS_IS_SWIZZLED_AMD);
.access = ACCESS_COHERENT | ACCESS_IS_SWIZZLED_AMD,
.align_mul = 16, .align_offset = const_off % 16u);
} else if (out_mode == ms_out_mode_var) {
unsigned write_mask_32 = write_mask;
if (store_val->bit_size > 32) {
@@ -754,7 +755,8 @@ ms_emit_attribute_ring_output_stores(nir_builder *b, const uint64_t outputs_mask
store_val = nir_trim_vector(b, store_val, store_val_components);
nir_store_buffer_amd(b, store_val, ring, zero, soffset, idx,
.memory_modes = nir_var_shader_out,
.access = ACCESS_COHERENT | ACCESS_IS_SWIZZLED_AMD);
.access = ACCESS_COHERENT | ACCESS_IS_SWIZZLED_AMD,
.align_mul = 16, .align_offset = 0);
}
}
src/amd/common/nir/ac_nir_prerast_utils.c
+4 -2
View File
@@ -508,7 +508,8 @@ ac_nir_store_parameters_to_attr_ring(nir_builder *b,
nir_store_buffer_amd(b, nir_vec(b, comp, 4), attr_rsrc, voffset, attr_offset, vindex,
.base = offset * 16,
.memory_modes = nir_var_shader_out,
.access = ACCESS_COHERENT | ACCESS_IS_SWIZZLED_AMD);
.access = ACCESS_COHERENT | ACCESS_IS_SWIZZLED_AMD,
.align_mul = 16, .align_offset = 0);
exported_params |= BITFIELD_BIT(offset);
}
@@ -536,7 +537,8 @@ ac_nir_store_parameters_to_attr_ring(nir_builder *b,
nir_store_buffer_amd(b, nir_vec(b, comp, 4), attr_rsrc, voffset, attr_offset, vindex,
.base = offset * 16,
.memory_modes = nir_var_shader_out,
.access = ACCESS_COHERENT | ACCESS_IS_SWIZZLED_AMD);
.access = ACCESS_COHERENT | ACCESS_IS_SWIZZLED_AMD,
.align_mul = 16, .align_offset = 0);
exported_params |= BITFIELD_BIT(offset);
}