diff --git a/src/amd/common/nir/ac_nir_lower_legacy_gs.c b/src/amd/common/nir/ac_nir_lower_legacy_gs.c
index 312cf6fbad4..09c97a73878 100644
--- a/src/amd/common/nir/ac_nir_lower_legacy_gs.c
+++ b/src/amd/common/nir/ac_nir_lower_legacy_gs.c
@@ -113,12 +113,21 @@ lower_legacy_gs_emit_vertex_with_counter(nir_builder *b, nir_intrinsic_instr *in
          /* extend 8/16 bit to 32 bit, 64 bit has been lowered */
          nir_def *data = nir_u2uN(b, output, 32);
 
+         unsigned align_mul = 4;
+         unsigned align_offset = 0;
+         if (nir_src_is_const(intrin->src[0])) {
+            unsigned v_const_offset = base + nir_src_as_uint(intrin->src[0]) * 4;
+            align_mul = 16;
+            align_offset = v_const_offset % align_mul;
+         }
+
          nir_store_buffer_amd(b, data, gsvs_ring, voffset, soffset, nir_imm_int(b, 0),
                               .access = ACCESS_COHERENT | ACCESS_NON_TEMPORAL |
                                         ACCESS_IS_SWIZZLED_AMD,
                               .base = base,
                               /* For ACO to not reorder this store around EmitVertex/EndPrimitve */
-                              .memory_modes = nir_var_shader_out);
+                              .memory_modes = nir_var_shader_out,
+                              .align_mul = align_mul, .align_offset = align_offset);
       }
    }
 
diff --git a/src/amd/common/nir/ac_nir_lower_ngg_mesh.c b/src/amd/common/nir/ac_nir_lower_ngg_mesh.c
index 679a0e89728..2e4428efe29 100644
--- a/src/amd/common/nir/ac_nir_lower_ngg_mesh.c
+++ b/src/amd/common/nir/ac_nir_lower_ngg_mesh.c
@@ -330,7 +330,8 @@ ms_store_arrayed_output(nir_builder *b,
                            .base = const_off + param_offset * 16,
                            .write_mask = write_mask,
                            .memory_modes = nir_var_shader_out,
-                           .access = ACCESS_COHERENT | ACCESS_IS_SWIZZLED_AMD);
+                           .access = ACCESS_COHERENT | ACCESS_IS_SWIZZLED_AMD,
+                           .align_mul = 16, .align_offset = const_off % 16u);
    } else if (out_mode == ms_out_mode_var) {
       unsigned write_mask_32 = write_mask;
       if (store_val->bit_size > 32) {
@@ -754,7 +755,8 @@ ms_emit_attribute_ring_output_stores(nir_builder *b, const uint64_t outputs_mask
       store_val = nir_trim_vector(b, store_val, store_val_components);
       nir_store_buffer_amd(b, store_val, ring, zero, soffset, idx,
                            .memory_modes = nir_var_shader_out,
-                           .access = ACCESS_COHERENT | ACCESS_IS_SWIZZLED_AMD);
+                           .access = ACCESS_COHERENT | ACCESS_IS_SWIZZLED_AMD,
+                           .align_mul = 16, .align_offset = 0);
    }
 }
 
diff --git a/src/amd/common/nir/ac_nir_prerast_utils.c b/src/amd/common/nir/ac_nir_prerast_utils.c
index 2604db0b3f6..316852a52e7 100644
--- a/src/amd/common/nir/ac_nir_prerast_utils.c
+++ b/src/amd/common/nir/ac_nir_prerast_utils.c
@@ -508,7 +508,8 @@ ac_nir_store_parameters_to_attr_ring(nir_builder *b,
       nir_store_buffer_amd(b, nir_vec(b, comp, 4), attr_rsrc, voffset, attr_offset, vindex,
                            .base = offset * 16,
                            .memory_modes = nir_var_shader_out,
-                           .access = ACCESS_COHERENT | ACCESS_IS_SWIZZLED_AMD);
+                           .access = ACCESS_COHERENT | ACCESS_IS_SWIZZLED_AMD,
+                           .align_mul = 16, .align_offset = 0);
 
       exported_params |= BITFIELD_BIT(offset);
    }
@@ -536,7 +537,8 @@ ac_nir_store_parameters_to_attr_ring(nir_builder *b,
       nir_store_buffer_amd(b, nir_vec(b, comp, 4), attr_rsrc, voffset, attr_offset, vindex,
                            .base = offset * 16,
                            .memory_modes = nir_var_shader_out,
-                           .access = ACCESS_COHERENT | ACCESS_IS_SWIZZLED_AMD);
+                           .access = ACCESS_COHERENT | ACCESS_IS_SWIZZLED_AMD,
+                           .align_mul = 16, .align_offset = 0);
 
       exported_params |= BITFIELD_BIT(offset);
    }