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Author SHA1 Message Date
Dave Airlie 521dc42e6c llvmpipe: handle stride properly on lvp udmabuf imports 
The import data comes in via the fd import, but we need to make
sure to store the row stride value here.

Fixes: c44d65a467 ("lp: only map dt buffer on import from dmabuf")
Reviewed-by: Lucas Fryzek <lfryzek@igalia.com>
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30839>
 2024-08-26 22:53:12 +00:00
Dave Airlie 7db16e7cdd radv: turn video decode/encode on for VCN4 with latest fw 
With the latest fw in the linux-firmware repo, navi3x passes
all the CTS tests.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30837>
 2024-08-26 22:19:09 +00:00
Dave Airlie 4255bbd958 radv: move video decode enable test into a flag 
This makes it easier to start conditionalising this on fw releases.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30837>
 2024-08-26 22:19:09 +00:00
Benjamin Cheng 95a980b61f radv/video: add event support for VCN4 
This was the main missing piece for passing vulkan video CTS
as the video firmwares couldn't do proper vulkan events.

With new enough firmware this is now possible.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30837>
 2024-08-26 22:19:09 +00:00
Víctor Manuel Jáquez Leal c340862555 frontends/va: Don't return P010/P016 as surface formats when encoding 
This is almost a complete revert of 0eccd158 (!3285), since it was a
driver fix for a client bug. vaapih265enc should be fixed rather adding
a workaround that breaks the logic of API, since vaQuerySurfaceAttributes
depends only on config parameter, which defines the rt format.

You can verify it with vadumpcap https://github.com/fhvwy/vadumpcaps

Signed-off-by: Victor Jaquez <vjaquez@igalia.com>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19443>
 2024-08-26 22:01:46 +00:00
Mike Blumenkrantz 786be05df3 dril: add zink stub 
ironically this was the only driver left out

Fixes: 3de62b2f9a ("gallium/dril: Compatibility stub for the legacy DRI loader interface")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30851>
 2024-08-26 21:08:58 +00:00
Mike Blumenkrantz 7255c5e108 ci: add a660 flake 
https://gitlab.freedesktop.org/mesa/mesa/-/jobs/62739168

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30857>
 2024-08-26 20:42:22 +00:00
Assadian, Navid cb32bcd3fe amd/vpelib: Add 420 semi-planar 12bit handling 
Adds semi-Planar 420 12 bits formats.

Reviewed-by: Roy Chan <roy.chan@amd.com>
Acked-by: Alan Liu <haoping.liu@amd.com>
Signed-off-by: Navid Assadian <navid.assadian@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30715>
 2024-08-26 19:57:15 +00:00
Brendan fcad791d07 amd/vpelib: Create virtual stream concept 
[Why]
Need to create streams that don't come from input params (ex. for bg
gen) to prepare for future concepts.

[How]
Add enum for stream type, create helper functions to populate virtual
streams, and add custom functions where virtual stream function varies
from input stream function.

Reviewed-by: Roy Chan <roy.chan@amd.com>
Acked-by: Alan Liu <haoping.liu@amd.com>
Signed-off-by: Brendan Leder <brendansteve.leder@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30715>
 2024-08-26 19:57:14 +00:00
Lin, Ricky b670701b65 amd/vpelib: Increase the CD field in vpe descriptor programming 
Introduce the vpe desc writer hook.

Co-authored-by: Roy Chan <roy.chan@amd.com>
Reviewed-by: Roy Chan <roy.chan@amd.com>
Acked-by: Alan Liu <haoping.liu@amd.com>
Signed-off-by: Ricky Lin <ricky.lin@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30715>
 2024-08-26 19:57:14 +00:00
Shih, Jude cb9175a7af amd/vpelib: Update Plane Descriptor Writer 
Refactor to support new plane descriptor hook, and update enum
vpe_scan_direction.

Co-authored-by: Jesse Agate <jesse.agate@amd.com>
Co-authored-by: Roy Chan <roy.chan@amd.com>
Reviewed-by: Roy Chan <roy.chan@amd.com>
Acked-by: Alan Liu <haoping.liu@amd.com>
Signed-off-by: Jude Shih <shenshih@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30715>
 2024-08-26 19:57:14 +00:00
Patel, Utpal 18dae30b17 amd/vpelib: Add resource function hooks for checking support 
Add function hooks for checking support including rotation, background
color, DCC capability and input/output support check.

Reviewed-by: Roy Chan <roy.chan@amd.com>
Acked-by: Alan Liu <haoping.liu@amd.com>
Signed-off-by: Utpal Patel <utpal.patel@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30715>
 2024-08-26 19:57:14 +00:00
Alan Liu 06097ad64d amd/vpelib: Remove unused structs 
Remove the definition of unused structs:
- struct x_axis_config
- struct point_config
- struct curve_points32
- struct lut_point
- struct pwl_parameter2

Reviewed-by: Krunoslav Kovac <krunoslav.kovac@amd.com>
Acked-by: Alan Liu <haoping.liu@amd.com>
Signed-off-by: Alan Liu <haoping.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30715>
 2024-08-26 19:57:14 +00:00
Chang, Tomson 6483c2c786 amd/vpelib: Add and fix collaborate sync data 
[Why&How]
The original implementation always have sync data == 1.
Make it increasing with some 4 bits in random to help debugging
collaborate sync issues across multiple contexts.

Reviewed-by: Roy Chan <roy.chan@amd.com>
Acked-by: Alan Liu <haoping.liu@amd.com>
Signed-off-by: Tomson Chang <tomson.chang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30715>
 2024-08-26 19:57:14 +00:00
Lin, Ricky 015b1b52c8 amd/vpelib: Remove extra collaborate sync commands in IB 
Remove extra collaborate sync commands and fix coding format.

Co-authored-by: Roy Chan <roy.chan@amd.com>
Reviewed-by: Roy Chan <roy.chan@amd.com>
Acked-by: Alan Liu <haoping.liu@amd.com>
Signed-off-by: Ricky Lin <ricky.lin@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30715>
 2024-08-26 19:57:14 +00:00
Lin, Ricky e9e2fe389f amd/vpelib: Use VPE_IP_LEVEL_1_0 for VPE IP 6.1.3 
Use VPE_IP_LEVEL_1_0 for VPE IP version 6.1.0 and 6.1.3.

Reviewed-by: Tomson Chang <tomson.chang@amd.com>
Acked-by: Alan Liu <haoping.liu@amd.com>
Signed-off-by: Ricky Lin <ricky.lin@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30715>
 2024-08-26 19:57:14 +00:00
Patel, Utpal 73d112f372 amd/vpelib: Add input pixel format support 
Add input pixel format support for VPE.

Signed-off-by: Utpal Patel <utpal.patel@amd.com>
Reviewed-by: Jesse Agate <jesse.agate@amd.com>
Acked-by: Alan Liu <haoping.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30715>
 2024-08-26 19:57:14 +00:00
Hsieh, Mike 0164bfda65 amd/vpelib: Add cache mechanism for 3D Lut command 
[WHY & HOW]
Converting 3D Lut parameters into vpe command takes time.
3D Lut will not change every frame, by adding cache mechanism can improve effeciency.

Reviewed-by: Tomson Chang <tomson.chang@amd.com>
Acked-by: Alan Liu <haoping.liu@amd.com>
Signed-off-by: Mike Hsieh <mike.hsieh@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30715>
 2024-08-26 19:57:14 +00:00
Kovac, Krunoslav 9817793cd9 amd/vpelib: Reuse existing float to reg format conversion 
Remove vpe_fixpt_from_float and use existing conversion
for double(float)->reg custom 1.6.12 format.

Reviewed-by: Roy Chan <roy.chan@amd.com>
Acked-by: Alan Liu <haoping.liu@amd.com>
Signed-off-by: Krunoslav Kovac <krunoslav.kovac@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30715>
 2024-08-26 19:57:14 +00:00
Eric Engestrom f79c80e6d6 turnip/ci: document all the a750 flakes seen in the last week 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30856>
 2024-08-26 19:41:12 +00:00
Eric Engestrom 22bd67a16d zink+nvk/ci: document all the flakes seen in the last week 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30856>
 2024-08-26 19:41:12 +00:00
Eric Engestrom 6ab8e089bd zink+nvk/ci: document new variant of test failing 
Failing since a commit in the fef77e1d...7b32df69 range

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30856>
 2024-08-26 19:41:12 +00:00
Rhys Perry dea1fedf51 aco/tests: add more VALUMaskWriteHazard tests 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30818>
 2024-08-26 19:16:34 +00:00
Rhys Perry 11262a01ce aco: preserve bitsets after a lane mask is written 
fossil-db (navi31):
Totals from 4840 (6.10% of 79395) affected shaders:
Instrs: 13733449 -> 13761177 (+0.20%); split: -0.00%, +0.21%
CodeSize: 71997868 -> 72102520 (+0.15%); split: -0.00%, +0.15%
Latency: 128385177 -> 128408780 (+0.02%); split: -0.00%, +0.02%
InvThroughput: 21105847 -> 21109475 (+0.02%); split: -0.00%, +0.02%
VALU: 7741209 -> 7741210 (+0.00%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Backport-to: 24.1
Backport-to: 24.2
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30818>
 2024-08-26 19:16:34 +00:00
Rhys Perry 61e73c2323 aco: check SALU writing lanemask later for VALUMaskWriteHazard 
This should be done after reads are checked and
sgpr_read_by_valu_as_lanemask_then_wr_by_salu is reset. The old version
also skipped checking the reads if the write check passed.

fossil-db (navi31):
Totals from 193 (0.24% of 79395) affected shaders:
Instrs: 3212435 -> 3212735 (+0.01%)
CodeSize: 16462868 -> 16463848 (+0.01%); split: -0.00%, +0.01%
Latency: 19492377 -> 19492462 (+0.00%); split: -0.00%, +0.00%
InvThroughput: 4419705 -> 4419718 (+0.00%); split: -0.00%, +0.00%

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Backport-to: 24.1
Backport-to: 24.2
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30818>
 2024-08-26 19:16:34 +00:00
Rhys Perry b1ba7d1b99 aco: don't consider sa_sdst=0 before SALU write to fix VALUMaskWriteHazard 
LLVM does but that's probably a bug.

fossil-db (navi31):
Totals from 311 (0.39% of 79395) affected shaders:
Instrs: 380453 -> 381075 (+0.16%)
CodeSize: 1961012 -> 1964744 (+0.19%)
Latency: 4799095 -> 4800313 (+0.03%)
InvThroughput: 958358 -> 958904 (+0.06%)
VALU: 242322 -> 242633 (+0.13%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Backport-to: 24.1
Backport-to: 24.2
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30818>
 2024-08-26 19:16:34 +00:00
Rhys Perry 8f5ee70d85 aco: also consider VALU reads for VALUMaskWriteHazard 
fossil-db (navi31):
Totals from 9776 (12.31% of 79395) affected shaders:
Instrs: 19348258 -> 19383680 (+0.18%); split: -0.00%, +0.19%
CodeSize: 101223460 -> 101366964 (+0.14%); split: -0.01%, +0.15%
Latency: 172853115 -> 172866070 (+0.01%); split: -0.01%, +0.01%
InvThroughput: 27590468 -> 27592390 (+0.01%); split: -0.00%, +0.01%

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11550
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11436
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11337
Gitlab: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11738
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11741
Backport-to: 24.1
Backport-to: 24.2
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30818>
 2024-08-26 19:16:34 +00:00
Rhys Perry ee648326d9 aco: ignore exec and literals when mitigating VALUMaskWriteHazard 
LLVM ignores exec and literals don't seem to work in some cases.

fossil-db (navi31):
Totals from 2676 (3.37% of 79395) affected shaders:
Instrs: 10638979 -> 10646019 (+0.07%); split: -0.00%, +0.07%
CodeSize: 55929640 -> 55959416 (+0.05%); split: -0.00%, +0.06%
Latency: 107707408 -> 107712893 (+0.01%); split: -0.00%, +0.01%
InvThroughput: 18119843 -> 18120442 (+0.00%); split: -0.00%, +0.00%

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Backport-to: 24.1
Backport-to: 24.2
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30818>
 2024-08-26 19:16:34 +00:00
Eric Engestrom 75ab02068e kopper: only include loader_dri3_helper.h when xcb is enabled 
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11779
Fixes: f14ef0ee0a ("kopper: reuse dri3 functions")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30848>
 2024-08-26 18:34:31 +00:00
Valentine Burley 4cfaf10c10 llvmpipe: Only use udmabuf with libdrm 
It's possible to have the linux/udmabuf.h header but not libdrm in some setups, like under Termux.

Fixes: 112063a060 ("llvmpipe: Only use udmabuf if header is found")
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Lucas Fryzek <lfryzek@igalia.com>
Signed-off-by: Valentine Burley <valentine.burley@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30853>
 2024-08-26 17:57:44 +00:00
Alyssa Rosenzweig 4fa1709eaf asahi/clc: drop caps list 
I'll use whatever caps I dang well please.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30792>
 2024-08-26 15:04:00 +00:00
Alyssa Rosenzweig fc28ebcfa1 vtn: infer SpvCapabilityLinkage 
It is always implemented by vtn, and it is available to the shader
depending on the create_library option. Either way, no reason for the backend to
worry about this.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30792>
 2024-08-26 15:04:00 +00:00
Mary Guillemard 694e68f359 nak: Fix wrong encoding for F2FP cbuf and immediate forms 
F2FP.PACK_AB always uses src0 and src1, only F2FP.MERGE_C uses src1 and
src2.

This fixes "f32tof16" instruction test regression on vk3d.

Fixes: e19871bd6a ("nak: Use F2FP for nir_op_pack_half_2x16_split on SM86+")
Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30804>
 2024-08-26 13:55:00 +00:00
Daniel Schürmann 14de650d58 aco: call nir_copy_prop() and nir_opt_dce() before instruction selection 
Totals from 1037 (1.31% of 79395) affected shaders: (Navi21)

MaxWaves: 18760 -> 18960 (+1.07%)
Instrs: 4865258 -> 4860063 (-0.11%); split: -0.11%, +0.00%
CodeSize: 27094112 -> 27089224 (-0.02%); split: -0.06%, +0.04%
VGPRs: 68816 -> 68000 (-1.19%)
SpillVGPRs: 2140 -> 2105 (-1.64%)
Scratch: 4237312 -> 4234240 (-0.07%)
Latency: 55894512 -> 55748035 (-0.26%); split: -0.31%, +0.05%
InvThroughput: 11611286 -> 11372897 (-2.05%); split: -2.09%, +0.03%
VClause: 145331 -> 145285 (-0.03%); split: -0.04%, +0.01%
SClause: 150339 -> 150338 (-0.00%)
Copies: 472476 -> 468470 (-0.85%); split: -0.88%, +0.03%
Branches: 206562 -> 206067 (-0.24%); split: -0.24%, +0.00%
PreVGPRs: 61747 -> 61361 (-0.63%)
VALU: 3116434 -> 3112660 (-0.12%); split: -0.13%, +0.00%
SALU: 723154 -> 722887 (-0.04%); split: -0.04%, +0.01%
VMEM: 238656 -> 238586 (-0.03%)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30786>
 2024-08-26 12:59:00 +00:00
Juan A. Suarez Romero e030ab4bf2 vc4/ci: update expected results 
Add some regressions in vc4.

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30847>
 2024-08-26 12:41:10 +00:00
Eric Engestrom 07202111a6 ci/rules: make every job exist as manual in fork pipelines 
In forks, every job exists, but no job is automatically run.

Should help with the problem of users clicking on that tempting "play"
button GitLab offers and that has been causing a lot of issues with
wasted resources.

Downside is, users now have to use the `bin/ci/ci_run_n_monitor.sh`
script to be able to run a bunch of jobs at once.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25252>
 2024-08-26 11:49:34 +00:00
Collabora's Gfx CI Team e54440d15e Uprev Piglit to a3826de3c26a279599d15b018a9a3e75ca46f4f8 
https://gitlab.freedesktop.org/mesa/piglit/-/compare/6533b66878c8cb9361c554b7ff940518ab12c816...a3826de3c26a279599d15b018a9a3e75ca46f4f8

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30825>
 2024-08-26 11:01:58 +00:00
Lionel Landwerlin 1f9c40a8d1 anv: explicitly disable BT pool allocations at device init 
The default state doesn't seem well defined (or kernel driver bug
maybe?). Let's just set it to disabled on platforms where we're not
using it.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Found-by: Chuansheng Liu <chuansheng.liu@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30841>
 2024-08-26 10:34:31 +00:00
Erico Nunes 749d7e96bf lima/ppir: switch to derivative intrinsics 
Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30661>
 2024-08-26 09:53:35 +00:00
Samuel Pitoiset cc5d481f41 radv/ci: enable RADV_PERFTEST=transfer_queue on GFX9+ 
To avoid breaking this because it's not enabled by default.

There is a couple of failures because MSAA is still broken with SDMA.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30778>
 2024-08-26 09:26:52 +00:00
Samuel Pitoiset 731523a10b radv/ci: update flakes lists for NAVI21/VANGOGH 
Found these when I did a stress test with RADV_PERFTEST=transfer_queue
enabled but they are existing flakes.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30778>
 2024-08-26 09:26:52 +00:00
Dave Airlie 68cd36d9b4 radv/video: fix reporting video format props for encode. 
When encode isn't enabled, refuse the image usage, also use
the correct error on the decode check.

Fixes: 05cd42417f ("radv/video: enable video encoding behind perftest flag")
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30838>
 2024-08-26 08:49:54 +00:00
Samuel Pitoiset 7f7ecaf08c radv: optimize NOPs padding with DGC 
There is two different alignment requirements:
a) IB VA must be aligned to ib_alignment
b) IB size must be aligned to ib_pad_dw_mask

Though RADV was aligning DGC cmdbuf to ib_alignment always, but this is
unnecessary. Using the optimal padding size for DGC cmdbuf removes a
bunch of useless NOPs.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30768>
 2024-08-26 08:22:06 +00:00
Samuel Pitoiset a7547a9781 radv/amdgpu: assert that the DGC IB VA is correctly aligned 
It must be aligned to what the kernel returns.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30768>
 2024-08-26 08:22:06 +00:00
David Heidelberg 8f8a51ac5c etnaviv: build dependency for the etnaviv tests 
Resolves failures as:
... -o src/etnaviv/isa/tests/etnaviv_disasm.p/disasm.cpp.o -c ../src/etnaviv/isa/tests/disasm.cpp
In file included from ../src/etnaviv/isa/tests/disasm.cpp:12:
../src/etnaviv/isa/asm.h:15:10: fatal error: etnaviv/isa/enums.h: No such file or directory
   15 | #include "etnaviv/isa/enums.h"
      |          ^~~~~~~~~~~~~~~~~~~~~

Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11740
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Signed-off-by: David Heidelberg <david@ixit.cz>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30829>
 2024-08-26 08:09:15 +00:00
David Heidelberg 43bff3b9eb etnaviv: rename enums_h appropriately 
Needed for the follow-up change.

Cc: mesa-stable
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Signed-off-by: David Heidelberg <david@ixit.cz>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30829>
 2024-08-26 08:09:14 +00:00
Qiang Yu 48a49c4e04 radeonsi: enable KHR_shader_subgroup 
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30610>
 2024-08-26 10:46:21 +08:00
Qiang Yu 1ee612e1ac radeonsi: use wave64 for KHR_shader_subgroup enabled shader 
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30610>
 2024-08-26 10:46:20 +08:00
Qiang Yu a78d1d49e6 radeonsi: consider both stages to determine merged shader wave_size 
Previously we determine wave_size of merged shader stages separately,
and ignore the condition which may cause them to be different.

Now we determine the wave_size of the TCS/GS part first, then use the
wave_size for VS/TES part. So that we can condider the previous shader
stage's information when determine the wave_size of TCS/GS, and two
stages in the merged shader can affect each other's wave_size.

This requires si_shader_selector to have two kinds of main part for
wave32 and wave64 when part mode, to be combined with other shader
part with various wave size.

This also enables merged shader stages with different
si_shader_info->has_divergent_loop to use wave32. We'll add another
condition for KHR_shader_subgroup latter.

Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30610>
 2024-08-26 10:46:20 +08:00
Qiang Yu 196d91ed78 radeonsi: remove NULL check in si_determine_wave_size 
This function is always called with non-NULL shader now.

Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30610>
 2024-08-26 10:46:20 +08:00