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Author SHA1 Message Date
Samuel Pitoiset
4fc856af98 radv: fix caching on-demand meta shaders 
This switches to disk_cache instead of our own mechanism which only
stored meta shaders when the logical was destroyed.

Meta shaders are still stored separately from the application shaders
because they are common to all applications on a given GPU/Mesa version.
The default cache is 32MiB which should be large enough.

This fixes massive stuttering in FF7 Rebirth but all apps are
technically affected.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33370>
 2025-02-05 16:30:27 +00:00
Samuel Pitoiset
9d03c1afe0 vulkan/runtime: allow to use a different disk cache 
Instead of using the default one provided by the physical device.
This will be used by RADV to store meta shaders to a separate single
cache file.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33370>
 2025-02-05 16:30:27 +00:00
Samuel Pitoiset
30961b2bfe util/disk_cache: add a new helper to create a disk cache 
This will be used by RADV to store the meta shaders to a separate
cache directory.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33370>
 2025-02-05 16:30:27 +00:00
Job Noorman
8404e7428b ir3: fix emitting descriptor prefetches at end of preamble 
The fix in e7ac1094f6 to emit preamble defs in the correct block would
move the cursor of the builder that is later used to insert descriptor
prefetches, emitting them at the wrong place. Fix this by resetting the
cursor before emitting the prefetches.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Fixes: e7ac1094f6 ("ir3: rematerialize preamble defs in block dominated by sources")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33399>
 2025-02-05 14:58:38 +00:00
Valentine Burley
e192d7d615 intel/ci: Update expectations for Xe 
Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33282>
 2025-02-05 14:01:03 +00:00
Valentine Burley
12ddff54ba intel/ci: Use INTEL_XE_IGNORE_EXPERIMENTAL_WARNING to reduce warnings 
Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33282>
 2025-02-05 14:01:03 +00:00
Valentine Burley
0d1fa0f1a3 intel/dev: Provide a toggle to avoid warnings about unsupported devices 
Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33282>
 2025-02-05 14:01:03 +00:00
Valentine Burley
fcd5d25888 intel/ci: Load Xe instead of i915 on ADL 
Xe doesn't probe on ADL without being explicitly forced through cmdline
arguments.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33282>
 2025-02-05 14:01:03 +00:00
Valentine Burley
93c5abd32b intel/ci: Add newer i915/ADL-P firmware to rootfs 
Add updated Alder Lake P firmware directly to the rootfs, as it is newer
than the version available in the Debian package. This is required for
the Xe kernel driver and is recommended for i915.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33282>
 2025-02-05 14:01:03 +00:00
Valentine Burley
f736f19642 intel/ci: Drop redundant BOOT_METHOD variables 
The BOOT_METHOD is defined in .intel-common-test, which every Intel
job inherits, including the zink jobs.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33282>
 2025-02-05 14:01:03 +00:00
Valentine Burley
b2105fe162 ci/lava: Allow passing extra cmdline arguments 
The LAVA_CMDLINE variable is appended to extra_nfsroot_args.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33282>
 2025-02-05 14:01:03 +00:00
Valentine Burley
9950dfcd80 ci: Use new kernel with Intel Xe driver 
The only change since the previous kernel is the enabling of
CONFIG_DRM_XE.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33282>
 2025-02-05 14:01:03 +00:00
Valentine Burley
8a54823db9 ci/intel-gpu-freq: Add Xe support 
Intel switched to exclusively using per-tile sysfs interfaces in Xe.
The locations and names of the sysfs attributes also changed compared
to i915, so update the intel-gpu-freq.sh script to work with both KMDs.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33282>
 2025-02-05 14:01:03 +00:00
Mary Guillemard
e3b8d1da6d panvk: Disallow unknown GPU models early in physical device init 
We rely on the panfrost_model details around the codebase, if it's not
known this is a problem.

As a result, we will now disallow anything that isn't known like what
we do on Gallium.

Fixes: c95ef9e323 ("panvk: Fix NULL deref on model name when device isn't supported")
Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Suggested-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33371>
 2025-02-05 13:30:29 +00:00
Mary Guillemard
0e7ac7d65f panfrost: Properly name CSF instruction UMIN32 source 0 
Was named source 2, but it's actually source 0.

Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33371>
 2025-02-05 13:30:29 +00:00
Mary Guillemard
7bb6ebe938 pan/decode: Fix indirect branch calculation for 64-bit 
THe enum variant for u64 was actually 32-bit making all 64-bit operation
wrong.

Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Fixes: 7d0dc3d30c ("pan/decode: Add a helper to print CS binaries without interpreting them")
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33371>
 2025-02-05 13:30:29 +00:00
Mary Guillemard
135aeddc9b pan/bi: Use 2D dimension with TEX_FETCH with CUBE on Valhall 
TEX_FETCH doesn't have the CUBE dimension, this was working on v9 and
v10 but this fails on Avalon.

Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Fixes: ce52b6d359 ("pan/bi: Rework indices for tex on Valhall")
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33371>
 2025-02-05 13:30:29 +00:00
Mary Guillemard
c36326d3af pan/bi: Remove b3210 from valid swizzle 
This was removed on v11, we currently don't use it so to ensure no one
start using it, let's just mark it as reserved.

Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33371>
 2025-02-05 13:30:29 +00:00
Mary Guillemard
b00c09b920 pan/bi: Fix invalid CLPER encoding 
This src1 expect lanes, isn't widen and have a size of 8-bit (5-bit on
Valhall, 4-bit on Avalon)

We also now disallow swizzle lowering on it. (even on Bifrost)

Fixes: 316486dd9f ("pan/va: Add initial ISA.xml for Valhall")
Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33371>
 2025-02-05 13:30:29 +00:00
Mary Guillemard
637cb0a993 pan/bi: Remove shift lanes invalid encodings 
We were wrongly defining values that select more than one byte.

The swizzle used for H01 was working fine for v9 and v10, but this
generate an invalid encoding on Avalon.

This fixes this by using B00 variant as we are only using 8-bit sources.

Fixes: f45654af59 ("pan/va: Add packing routines")
Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33371>
 2025-02-05 13:30:29 +00:00
Mary Guillemard
fbd5d58e36 pan/bi: Properly encode LEA_BUF_IMM 
We were hardcoding table 61 and index 0 for IDVS based usage and this
could have been misused.

Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Fixes: f45654af59 ("pan/va: Add packing routines")
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33371>
 2025-02-05 13:30:29 +00:00
Mary Guillemard
38a3cd8c76 panfrost: Fix PROGRESS_LOAD destination register 
The offset of dest should be 40, not 48.

Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Fixes: 486c341769 ("panfrost: Add architecture description XML for v10")
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33371>
 2025-02-05 13:30:29 +00:00
Mary Guillemard
05c2abcfea panfrost: Fix group priorities in drm-shim 
Those were supposed to use BITFIELD_BIT.

Fixes: 2237cff1af ("panfrost: Report default value for GROUP_PRIORITIES_INFO in drm-shim")
Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33371>
 2025-02-05 13:30:29 +00:00
Faith Ekstrand
555b8580ae nak: Fix cbuf textures 
Somewhere between writing c1510ad72e ("nak: Optimize bindless to cbuf
textures on Volta+") and me rebasing it a year later, we switched to
using the NV-specific ldc_nv intrinsic for cbuf loads.  It's basically
the same as load_ubo but we're detecting the wrong intrinsic so the
optimization does nothing.

Fixes: c1510ad72e ("nak: Optimize bindless to cbuf textures on Volta+")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33398>
 2025-02-05 13:02:46 +00:00
Erik Faye-Lund
4d86a1c928 pan/ci: add flaky tests to the flake-list 
These have been switching between failing and passing recently. Not
really sure what's going on here, but we don't want the CI to flip
randomly between failing and passing, so let's mark them as flakes.

Backport-to: 25.0
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33381>
 2025-02-05 12:38:16 +00:00
Erik Faye-Lund
6f70425ef5 panvk/ci: add back incorrectly removed crash 
Turns out, this was only fixed on G610, not on G52.

Fixes: f93a48e4e3 ("panfrost: fix hang by using MALI_PIXEL_KILL_WEAK_EARLY in color preload")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33381>
 2025-02-05 12:38:16 +00:00
Georg Lehmann
ed675272f4 nir/lower_poly_line_smooth: use intrinsics_pass 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33340>
 2025-02-05 11:23:35 +00:00
Georg Lehmann
998e2299f7 nir/lower_poly_line_smooth: don't reject fp16 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33340>
 2025-02-05 11:23:35 +00:00
Georg Lehmann
ff225dee67 radv: inline radv_nir_lower_poly_line_smooth 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33340>
 2025-02-05 11:23:35 +00:00
Georg Lehmann
b588b56078 radv: remove radv_should_lower_poly_line_smooth 
I think this was broken as there might be a store_output with
less than 4 components to a location that shouldn't be smoothed
anyway (i.e. not the first one).

nir_lower_poly_line_smooth now handles the case where the first location
doesn't have 4 components.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33340>
 2025-02-05 11:23:35 +00:00
Georg Lehmann
359ba65903 nir/lower_poly_line_smooth: support partial store_output 
RADV needs this to skip if there is no alpha component

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33340>
 2025-02-05 11:23:35 +00:00
Georg Lehmann
6c410456d9 nir/lower_poly_line_smooth: only smooth first color target 
The VK spec says:
coverage value is multiplied into the color location 0’s
alpha value after fragment shading

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33340>
 2025-02-05 11:23:34 +00:00
Georg Lehmann
534c2ceac8 nir/lower_poly_line_smooth: don't emit control flow 
The if is really short so it should really use a conditional select,
but this pass is called too late go through all the usual lowerings
and opts.

Foz-DB Navi21:
Totals from 1128 (1.42% of 79377) affected shaders:
MaxWaves: 29358 -> 29342 (-0.05%)
Instrs: 552306 -> 549668 (-0.48%); split: -0.58%, +0.10%
CodeSize: 2796392 -> 2782360 (-0.50%); split: -0.59%, +0.08%
Latency: 2574361 -> 2566482 (-0.31%); split: -0.47%, +0.16%
InvThroughput: 644047 -> 647500 (+0.54%); split: -0.18%, +0.72%
Copies: 37521 -> 36460 (-2.83%); split: -2.92%, +0.09%
Branches: 12009 -> 10157 (-15.42%)
VALU: 350886 -> 349199 (-0.48%); split: -0.64%, +0.16%
SALU: 104459 -> 105415 (+0.92%); split: -0.00%, +0.92%

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33340>
 2025-02-05 11:23:34 +00:00
Daniel Schürmann
1a8a643bbd aco/isel: track control flow divergence in loops more accurately 
We introduce two new variables, cf_context::in_divergent_cf and
cf_context::parent_loop.has_divergent_break, in order to determine
whether there is any other invocations on a different CF path.

Totals from 1305 (1.64% of 79395) affected shaders: (Navi31)

Instrs: 659211 -> 657815 (-0.21%); split: -0.22%, +0.01%
CodeSize: 3483228 -> 3477960 (-0.15%); split: -0.16%, +0.01%
VGPRs: 68820 -> 48048 (-30.18%)
Latency: 14197750 -> 14170767 (-0.19%); split: -0.26%, +0.07%
InvThroughput: 1619103 -> 1619826 (+0.04%); split: -0.02%, +0.07%
VClause: 12384 -> 12350 (-0.27%)
SClause: 26693 -> 26844 (+0.57%); split: -0.01%, +0.57%
Copies: 44994 -> 43535 (-3.24%); split: -3.26%, +0.02%
PreSGPRs: 49007 -> 48907 (-0.20%)
PreVGPRs: 32171 -> 32121 (-0.16%)
VALU: 349984 -> 349857 (-0.04%); split: -0.04%, +0.00%
SALU: 84252 -> 83988 (-0.31%); split: -0.32%, +0.00%
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33206>
 2025-02-05 10:54:21 +00:00
Daniel Schürmann
583c3586fe aco/isel: remove loop nest information from exec_info 
Since we never enter loops with an empty exec mask, and the
control flow is structured, we don't need to consider the
loop nest depth.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33206>
 2025-02-05 10:54:21 +00:00
Daniel Schürmann
a77258346c aco/isel: fix assumptions about potential empty exec mask in nested control flow 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33206>
 2025-02-05 10:54:21 +00:00
Daniel Schürmann
44216e035f aco/isel: add and use exec_info::empty() helper 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33206>
 2025-02-05 10:54:21 +00:00
Daniel Schürmann
8e8398832c aco/isel: use cf_context in loop_context to restore cf information 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33206>
 2025-02-05 10:54:21 +00:00
Daniel Schürmann
8b9c9fb904 aco/isel: use cf_context in if_context to restore cf information 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33206>
 2025-02-05 10:54:21 +00:00
Daniel Schürmann
c2bfc05d71 aco/isel: rename cf_context::has_divergent_branch 
Make it more consistent with cf_context::has_branch.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33206>
 2025-02-05 10:54:21 +00:00
Daniel Schürmann
0c5a91b9f2 aco/isel: move cf_info into separate struct cf_context 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33206>
 2025-02-05 10:54:21 +00:00
Daniel Schürmann
61fa007e48 aco/isel: fix empty exec tracking for uniform branches 
Totals from 5 (0.01% of 79395) affected shaders: (Navi31)

Instrs: 54730 -> 54715 (-0.03%)
CodeSize: 276928 -> 276852 (-0.03%)
Latency: 215212 -> 214874 (-0.16%)
InvThroughput: 40154 -> 40150 (-0.01%)
Copies: 6824 -> 6821 (-0.04%); split: -0.06%, +0.01%
Branches: 1625 -> 1615 (-0.62%)
SALU: 5682 -> 5678 (-0.07%)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33206>
 2025-02-05 10:54:21 +00:00
Benjamin Lee
bd32129c1a panvk: document missed extensions in new_features 
This should have been included in the commits that introduced the
extensions.

Signed-off-by: Benjamin Lee <benjamin.lee@collabora.com>
Fixes: 00fb0f5ec2 ("panvk: enable KHR_separate_depth_stencil_layouts")
Fixes: 935cadbc2e ("panvk: enable VK_KHR_depth_stencil_resolve")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33394>
 2025-02-05 10:46:48 +00:00
Valentine Burley
a4b8131255 zink/ci: Make zink-venus-lvp-full a nightly job 
The zink-venus-lvp-full job was intended to be a nightly job, but it
was missing the proper manual rules for that.

Fixes: 7bf4d6a4db ("zink/ci: Add a fraction for zink-venus-lvp")

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Reviewed-by: Martin Roukala <None>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33393>
 2025-02-05 10:25:01 +00:00
Lionel Landwerlin
a8b84e1898 anv: use A64 messages for push constants loads on Gfx12.5+ 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32895>
 2025-02-05 09:56:04 +00:00
Lionel Landwerlin
5c17299084 brw: enable A64 pulling of push constants 
This will be useful for pulling constants in device bound shaders. A64
allows us to put the constants anywhere.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32895>
 2025-02-05 09:56:04 +00:00
Lionel Landwerlin
0808125914 brw/anv: rework push constants for mesh/task shaders 
Now using the same model as the compute shader.

As a result we temporarily disable the use of the Inline register for
providing push constants on Task & Mesh shaders. Since that register
is also available on the compute shader we'll try to find a way to use
the same mechanism for all 3 shaders in another MR and bring back that
optimization.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32895>
 2025-02-05 09:56:04 +00:00
Lionel Landwerlin
a77e532248 anv: add a helper for getting gfx push constant addresses 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32895>
 2025-02-05 09:56:03 +00:00
Lionel Landwerlin
26347b4876 anv: use heap size to program generate state heap 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32895>
 2025-02-05 09:56:03 +00:00
Lionel Landwerlin
ddf64a7d95 anv: track the first 2MB of unused VA 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32895>
 2025-02-05 09:56:03 +00:00