012b7aab26
driconf: add workarounds for SPECviewperf13
...
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5459 >
2020-06-23 09:25:24 +00:00
ca719c6e30
glsl,driconf: add allow_glsl_120_subset_in_110 for SPECviewperf13
...
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5459 >
2020-06-23 09:25:24 +00:00
f8e8701cf1
radeonsi: replace ctx->screen with sscreen in si_flush_gfx_cs
...
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5506 >
2020-06-23 09:12:16 +00:00
470b319813
radeonsi: don't wait for idle at the end of gfx IBs
...
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5506 >
2020-06-23 09:12:16 +00:00
57606c2ab5
gitlab-ci: stop testing RADV with LLVM
...
ACO is going to be our default compiler soon and it seems useless
to waste CI resources for LLVM.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com >
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5543 >
2020-06-23 08:21:56 +00:00
0aca04afa5
aco: fix printing ASM on GFX6-7 again
...
Checking errno is actually wrong because it's only updated if
popen() fails (ie. NULL). One solution is to check if the first
line is empty.
Fixes: c95d258d1bsamuel.pitoiset@gmail.com >
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5591 >
2020-06-23 07:45:03 +00:00
e0518800a1
gitlab-ci: Update CTS runner
...
We need a newer version to be able to successfully run the OpenGL suites
in dEQP.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com >
Reviewed-by: Eric Anholt <eric@anholt.net >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5494 >
2020-06-23 06:59:27 +00:00
287bf5f208
gitlab-ci: Test virgl with Khronos' OpenGL CTS
...
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com >
Reviewed-by: Eric Anholt <eric@anholt.net >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5494 >
2020-06-23 06:59:27 +00:00
2102d5eda5
gitlab-ci: Add manual tests for Virgl using GLES on the host
...
The ones that run automatically will use big GL on the host.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com >
Reviewed-by: Eric Anholt <eric@anholt.net >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5494 >
2020-06-23 06:59:27 +00:00
4417e924bf
gitlab-ci: Run more dEQP tests for virgl
...
Llvmpipe seems to have become faster, and we can run more tests while
still being under 5 minutes per job.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com >
Reviewed-by: Eric Anholt <eric@anholt.net >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5494 >
2020-06-23 06:59:27 +00:00
a2d7f4fe5a
glthread: handle ARB_vertex_attrib_binding
...
This handles ARB_vertex_attrib_binding for vertex uploads correctly.
Before this, the extension might have led to crashes if non-VBO vertex
attribs were present.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5303 >
2020-06-23 06:41:37 +00:00
66c2c9c6a9
glthread: rename non_vbo_attrib_mask -> user_buffer_mask, attribs -> buffers
...
just a cleanup, no change in behavior
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5303 >
2020-06-23 06:41:37 +00:00
2bf425431d
glapi: fix incorrect param names in ARB_vertex_attrib_binding functions
...
no change in behavior
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5303 >
2020-06-23 06:41:37 +00:00
2b8b62c55b
ac/nir: fix 64-bit division for GL CTS
...
This fixes: KHR-GL45.gpu_shader_fp64.builtin.mod_*
Fixes: ba2ec1f3pierre-eric.pelloux-prayer@amd.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5531 >
2020-06-23 04:46:55 +00:00
3fec2f67c3
radeonsi: compact MRTs to save PS export memory space
...
If there are holes between color outputs (e.g. a shader exports MRT1, but
not MRT0), we can remove the holes by moving higher MRTs lower.
The hardware will remap the MRTs to their correct locations if we remove
holes in SPI_SHADER_COL_FORMAT but not CB_SHADER_MASK.
This is a performance optimization, but MRTs with holes are pretty rare,
so there is most likely no effect on any app.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5535 >
2020-06-23 00:23:51 -04:00
6ac99b9f39
anv: Bump the advertised patch version to 145
...
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5597 >
2020-06-22 23:24:25 +00:00
a9ee1b9cf9
vulkan: Update Vulkan XML and headers to 1.2.145
...
Acked-by: Dave Airlie <airlied@redhat.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5597 >
2020-06-22 23:24:25 +00:00
677c1bd055
docs: cat maintainer keys to a single file
...
The original issue asked for all the keys in a single file, but I didn't
do that because it's much easier to manage and verify the keys as
separate files, but sphinx doesn't provide a way to expose a folder so
we'd need to create an index.html and have it list all the keys
manually, which is very error prone.
At this point, we might as well just concatenate the keys and expose
a single file, so let's do that.
Signed-off-by: Eric Engestrom <eric@engestrom.ch >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5568 >
2020-06-22 23:07:16 +00:00
b4335aaf0e
docs: drop deleted file from extra sphinx files
...
Fixes: 3e37b7e6bberic@engestrom.ch >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5567 >
2020-06-22 23:06:00 +00:00
c72832e83c
anv: Make use of devinfo has_aux_map field
...
Reworks:
* Use device rather than physical_device for info. (Lionel)
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5572 >
2020-06-22 22:32:03 +00:00
8c36936832
iris: Make use of devinfo has_aux_map field
...
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5572 >
2020-06-22 22:32:03 +00:00
4be31ebb61
gitlab-ci: drop gettext from the build images
...
Suggested-by: Pierre-Eric Pelloux-Prayer <pelloux@gmail.com >
Signed-off-by: Eric Engestrom <eric@engestrom.ch >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5440 >
2020-06-22 21:50:12 +00:00
04e8eaf4e8
util: rename xmlpool.h to driconf.h
...
To make it clearer what it is and does.
Signed-off-by: Eric Engestrom <eric@engestrom.ch >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5440 >
2020-06-22 21:50:12 +00:00
2ef983dca6
driconf: drop now unused translation facility
...
Signed-off-by: Eric Engestrom <eric@engestrom.ch >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5440 >
2020-06-22 21:50:12 +00:00
b1f647a3b4
driconf: drop 9% swedish translation
...
Only 7 of the 72 strings are translated, and there doesn't seem to be
any effort to keep it updated.
Signed-off-by: Eric Engestrom <eric@engestrom.ch >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5440 >
2020-06-22 21:50:12 +00:00
0a19565592
driconf: drop 8% dutch translation
...
Only 6 of the 72 strings are translated, and there doesn't seem to be
any effort to keep it updated.
Signed-off-by: Eric Engestrom <eric@engestrom.ch >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5440 >
2020-06-22 21:50:12 +00:00
56d76859fa
driconf: drop 6% french translation
...
Only 4 of the 72 strings are translated, and there doesn't seem to be
any effort to keep it updated.
Signed-off-by: Eric Engestrom <eric@engestrom.ch >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5440 >
2020-06-22 21:50:12 +00:00
a029eafba3
driconf: drop 26% spanish translation
...
Only 19 of the 72 strings are translated, and there doesn't seem to be
any effort to keep it updated.
Signed-off-by: Eric Engestrom <eric@engestrom.ch >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5440 >
2020-06-22 21:50:12 +00:00
29ee6f6c6a
driconf: drop 15% german translation
...
Only 11 of the 72 strings are translated, and there doesn't seem to be
any effort to keep it updated.
Signed-off-by: Eric Engestrom <eric@engestrom.ch >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5440 >
2020-06-22 21:50:12 +00:00
ae7759eb21
driconf: drop 28% catalan translation
...
Only 20 of the 72 strings are translated, and there doesn't seem to be
any effort to keep it updated.
Signed-off-by: Eric Engestrom <eric@engestrom.ch >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5440 >
2020-06-22 21:50:12 +00:00
6e24047573
zink: use correct define value for reserved slot count in ntv
...
this is zero-indexed, so we need to include the zero index in the count
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5592 >
2020-06-22 21:19:18 +00:00
c323e0ddf3
intel/dev: Add device info for DG1
...
Reworks:
* Anuj: Set is_dg1
* Anuj: Add dg1 to gen_device_name_to_pci_device_id
* Anuj: Update simulator id
* Rafael: has_llc = false
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com >
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4956 >
2020-06-22 11:42:00 -07:00
37a724e4ae
anv/dg1: Don't use SET_TILING kernel uapi.
...
It is not available on discrete platforms anymore.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4956 >
2020-06-22 11:42:00 -07:00
e658835436
iris/bufmgr: Do not use map_gtt or use set/get_tiling on DG1
...
We are starting to see platforms that don't support the get/set tiling
uAPI. (For example, DG1.)
Additionally on DG1 we shouldn't be using the map_gtt anymore.
Let's add some asserts and make sure we don't take those paths
accidentally.
Rework:
* Jordan: Only apply for DG1, not all gen12
* Rafael: Use has_tiling_uapi
* Jordan: Copy has_tiling_uapi from devinfo
* Jordan: merge in "iris: Rework iris_bo_import_dmabuf() a little."
* Jordan: Continue to call get/set_tiling on modifier path
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4956 >
2020-06-22 11:42:00 -07:00
762e601f77
intel/devinfo: Add function to check for DRM_I915_GEM_GET_TILING.
...
Future (discrete) platforms won't have support for get/set tiling. This
function allows our drivers to query for that, by simply trying to get
the tiling from a dummy buffer.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4956 >
2020-06-22 11:42:00 -07:00
86617c08cc
intel/l3: Return the URB size from devinfo for DG1
...
We don't have any URB size set in the L3 config, since it's a fixed
value now. So just return the value that we know from gen_device_info.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com >
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4956 >
2020-06-22 11:42:00 -07:00
793b409241
intel/isl: Update mocs for DG1
...
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com >
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4956 >
2020-06-22 11:42:00 -07:00
3daa866751
intel/l3: Add DG1 L3 configuration
...
Reworks:
* Jordan: Make DG1 L3 config table empty
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com >
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com >
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4956 >
2020-06-22 11:41:59 -07:00
633dec7163
anv: Set L3 full way allocation at context init if L3 cfg is NULL
...
If the platform's default L3 config is NULL, then it now gets
initialized only at context init time, and cmd_buffer_config_l3 will
always return immediately.
Rework:
* Remove unneeded check on !cfg in cmd_buffer_config_l3 (Jason)
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4956 >
2020-06-22 11:41:59 -07:00
e2e0521ecb
iris/l3: Enable L3 full way allocation when L3 config is NULL
...
Reworks:
* Jordan: Check for cfg == NULL rather than is_dg1
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4956 >
2020-06-22 11:41:59 -07:00
6054b24f58
intel/l3: Allow platforms to have no l3 configurations
...
On some gen12 platforms we will use the L3FullWayAllocationEnable and
never reconfigure the L3 setup.
Suggested-by: Kenneth Graunke <kenneth@whitecape.org >
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Francisco Jerez <currojerez@riseup.net >
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4956 >
2020-06-22 11:41:59 -07:00
49fe43e15f
intel/l3: Don't rely on cfg entry URB size being 0 as a sentinal
...
An example entry with URB size being 0 is in the cnl list.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4956 >
2020-06-22 11:41:59 -07:00
f1fba99695
intel/devinfo: Add is_dg1 to device info
...
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4956 >
2020-06-22 11:41:55 -07:00
64ccb74028
turnip: Enable tessellationShader physical device feature
...
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5059 >
2020-06-22 14:35:46 +00:00
497671be35
ir3: Unconditionally enable MERGEDREGS on a6xx
...
As per discussion on !5059 , we don't see any particular reason as to
why MERGEDREGS should be disabled on HS/DS/GS, and none of the dEQP
tests (both VK and GL) fail when MERGEDREGS is enabled. In fact, some
of the VK dEQP tests fail when MERGEDREGS is disabled (e.g. tests
with shaders that employ a0.x). As a result, let's just enable
MERGEDREGS unconditionally on a6xx.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5059 >
2020-06-22 14:35:46 +00:00
7a836ec631
turnip: Force sysmem for tessellation
...
Tessellation is incompatible with HW binning (dEQP tests fail when
we set forcebin), so force sysmem when we finish recording a command
buffer that uses a tess pipeline.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5059 >
2020-06-22 14:35:46 +00:00
2718353b38
turnip: Support tess for draws
...
This commit adds tessellation support for draws. We store the IR3
patch type in tu_pipeline so we can use it in tu_emit_draw_*. We then
convert the IR3 patch type to the native adreno patch type and set
the appropriate reg values.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5059 >
2020-06-22 14:35:46 +00:00
08aaa3d4c4
turnip: Emit HS/DS user consts as draw states
...
Just like VS/GS/FS.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5059 >
2020-06-22 14:35:45 +00:00
8cb226b258
turnip: Update VFD_CONTROL with tess system values
...
Support for TessCoord, PatchID, TCSHeader.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5059 >
2020-06-22 14:35:45 +00:00
f08a80dcd4
turnip: Allocate tess BOs as a function of draw size
...
To store tess outputs, the HS stg's into two buffers, one for
per-vertex/per-patch output variables (tess_param) and one for
TessLevelInner/Outer (tess_factor). The addresses of these buffers
are uploaded as consts to the HS/DS and the tess_factor iova is
written to REG_A6XX_PC_TESSFACTOR_ADDR. While the sizes of these
buffers are a function of vetex count and patch count, allocation is
relatively straightforward on freedreno- just keep track of the max
required buffer size for the entire batch and allocate before batch
submit.
In Vulkan, however, a given pipeline can be bound multiple times
across any number of command buffers, each drawing with a different
number of vertices. One solution is to track the max buffer size for
the entire command buffer (similar to fd_batch) and on
vkEndCommandBuffer, allocate appropriately sized tess BOs. Since the
tess BOs addresses are emitted as part of the pipeline state setup
(e.g. PKT4 to REG_A6XX_PC_TESSFACTOR_ADDR), we need to create a new
state group independent of a specific pipeline and parameterize its
IB with the command buffer specific tess BO iovas.
Without a larger refactor, the simplest way to do this is just to
emit per-draw call consts and leverage scratch_bo to re-use buffers.
This way we won't have to store and rewrite earlier packets in the
command stream on vkEndCommandBuffer.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5059 >
2020-06-22 14:35:45 +00:00
Marek Olšák