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Author SHA1 Message Date
Jason Ekstrand 4ef7b074e7 intel/isl: Indent uncompressed surface code 
We're about to add separate code for Yf/Ys and this helps keep the diff
reasonable.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
 2023-09-01 23:22:17 +00:00
Jason Ekstrand 9a4e9848ad intel/isl: Fill out the correct phys_total_extent for Ys/Yf/Tile64 
With these tilings, everything is aligned to a tile and the tiled
surface size calculations will handle the array stride for us.  We need
to provide an accurate 4D size so that 3D and multisampled images get
tiled correctly.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
 2023-09-01 23:22:17 +00:00
Jason Ekstrand 9421998e95 intel/isl: Use the depth field of phys_level0_sa for GFX4_2D 3D surfaces 
This makes things a tiny bit stickier in isl_calc_phys_total_extent_el
but will be worth it when we enable Yf and Ys.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
 2023-09-01 23:22:17 +00:00
Lionel Landwerlin 390d53e13f isl: disallow TileYs/Yf on 3D storage images on Gfx9/11 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
 2023-09-01 23:22:17 +00:00
Lionel Landwerlin 15648dcbba isl: add a usage flag to request 2D/3D compatible views 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
 2023-09-01 23:22:17 +00:00
Lionel Landwerlin 7c5015e181 isl: disable Yf/Ys/Tile64 tilings for 1D images 
The ICL+ PRMs show that this is not a supported thing anymore for
Ys/Yf and there isn't really much use for it in Vulkan/Sparse.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
 2023-09-01 23:22:17 +00:00
Lionel Landwerlin 6cde6b1d1a intel/isl: Disallow Yf, Ys and Tile64 for 3D depth/stencil surfaces 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
 2023-09-01 23:22:17 +00:00
Jason Ekstrand 911832e9cf intel/isl: Implement correct tile size calculations for Ys/Yf 
The tile size calculations use a clever bit of math to make them short
and simple.  We add unit tests to assert that they identically match the
tables in the PRM.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
 2023-09-01 23:22:17 +00:00
Jason Ekstrand e230ef329b intel/isl: Add ICL variants of Yf and Ys tiling 
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
 2023-09-01 23:22:17 +00:00
Jason Ekstrand fa625aea3d intel/isl: Rename ISL_TILING_Yf/s to ISL_TILING_SKL_Yf/s 
The Yf and Ys tilings change a bit between SKL and later generations so
we have to be able to distinguish between them.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
 2023-09-01 23:22:17 +00:00
Lionel Landwerlin 298e8dee61 isl: program 3DSTATE_HIER_DEPTH_BUFFER_BODY::TiledMode as documented 
Since this value is 0, it doesn't change anything, but it's just good
practice like we did for Gfx12.5 right above.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
 2023-09-01 23:22:17 +00:00
Lionel Landwerlin 3e9f366b70 genxml/gfx12: rename Tiled Resource Mode 
To match documentation.

BSpec 46965

TGL PRMs, Volume 2d: Command Reference: Structures, 3DSTATE_HIER_DEPTH_BUFFER_BODY

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
 2023-09-01 23:22:17 +00:00
Lionel Landwerlin cc985bb2ad genxml/gfx11: remove Tiled Resource Mode field from HIER_DEPTH_BUFFER 
This field doesn't exist according to documentation. Only a MBZ.

BSpec 6511

ICL PRMs, Volume 2a - Command Reference: Instructions (Command
Opcodes) 3DSTATE_HIER_DEPTH_BUFFER

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
 2023-09-01 23:22:16 +00:00
Lionel Landwerlin 34d5db0583 anv: add missing ISL storage usage 
ISL makes a bunch of decision on programming (MOCS,
RENDER_SURFACE_STATE values) based on this flag. It's important to set
it if we're going to use an image as storage.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
 2023-09-01 23:22:16 +00:00
Matt Turner 28c1053c07 intel: Allow using intel_clc from the system 
With -Dintel-clc=system, the build system will search for an `intel_clc`
binary and use it instead of building `intel_clc` itself.

This allows Intel Vulkan ray tracing support to be built when cross
compiling without terrible hacks (that would otherwise be necessary due
to `intel_clc`'s dependence on SPIRV-LLVM-Translator, libclc, clang, and
LLVM).

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24983>
 2023-09-01 21:36:02 +00:00
Karol Herbst 5263802618 rusticl/memory: do not verify pitch for IMAGE1D_BUFFER 
Devices might report an image_pitch_alignment of 0 leading to a division
by 0 trap.

Fixes: 06daa03c5c ("rusticl: Implement spec for cl_khr_image2d_from_buffer")
Signed-off-by: Karol Herbst <git@karolherbst.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24993>
 2023-09-01 20:06:30 +00:00
Eric Engestrom a8c7a2fb69 ci/amd: split the polaris10 rules into one for each farm 
There is now one polaris10 in each farm, so we need two rules for which
one to use.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24996>
 2023-09-01 19:35:33 +00:00
Mark Janes 0f291cb6c0 intel: allow reduced memory usage for INTEL_MEASURE 
The default batch size was increased to support large numbers of
INTEL_MEASURE snapshots for complex workloads.  Some titles create
large numbers of small secondary command buffers, and quickly exhaust
memory.  An example of this is Dota2, where INTEL_MEASURE increases
the memory usage by a factor of 20.

Allow the user to specify smaller batch sizes and buffer sizes.

Reviewed-by: Felix DeGrood <felix.j.degrood@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24860>
 2023-09-01 18:50:24 +00:00
Georg Lehmann cda5784eb3 aco: use v_cvt_f32_ubyte for signed casts too 
The extract is always positive, so signed vs unsigned conversion doesn't matter.

Foz-DB GFX11:
Totals from 167 (0.13% of 133461) affected shaders:
Instrs: 401631 -> 401225 (-0.10%)
CodeSize: 2107256 -> 2104344 (-0.14%)
VGPRs: 13320 -> 13332 (+0.09%)
Latency: 6468063 -> 6467241 (-0.01%)
InvThroughput: 801854 -> 801653 (-0.03%)
Copies: 13926 -> 13927 (+0.01%); split: -0.08%, +0.09%

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24893>
 2023-09-01 17:21:57 +00:00
Nanley Chery 144c2d4e4a anv: Initialize the clear color more often for FCV 
Instead of only initializing the clear color when the first subresource
is accessed, initialize it for every FCV-enabled subresource. This is
needed because writes to any subresource may be converted to fast
clears.

Now that init_fast_clear_color is called for every subresource, we take
care not to stomp on the fast-clear-tracking state of the first
subresource by moving the code which updates it outside of
init_fast_clear_color.

Now init_fast_clear_color does just what it says: initializes the fast
clear color.

This fixes the regression introduced with commit 57445adc89,
("anv: Re-enable CCS_E on TGL+").

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8461
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24857>
 2023-09-01 16:34:22 +00:00
Samuel Pitoiset 223d00fe0a radv/ci: re-enable vkcts-polaris10-valve 
This was disabled a long time ago because of unknown GPU hangs during
boot but it seems stable again for some reasons.

This also bumps the job timeouts to make sure it will be able to finish.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24968>
 2023-09-01 15:14:58 +00:00
Karol Herbst 46c17a8e54 rusticl/queue: properly implement clCreateCommandQueueWithProperties 
It didn't do any of the error checking, but it was supposed to be. Also
the error checking was slightly wrong and we should return
CL_INVALID_QUEUE_PROPERTIES instead of CL_INVALID_VALUE for unsupported
properties.

Signed-off-by: Karol Herbst <git@karolherbst.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24991>
 2023-09-01 13:51:22 +00:00
Samuel Pitoiset 969f7b97fd zink/ci: add zink-radv-polaris10-valve 
This introduces Zink/RADV testing on Polaris10!

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24976>
 2023-09-01 12:52:42 +00:00
Feng Jiang a1a2aac3a3 meson: Move video to separate section in meson configuration summary 
Since the video configuration is shared by multiple video APIs, not
just vulkan, move it to a separate section.

Signed-off-by: Feng Jiang <jiangfeng@kylinos.cn>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24598>
 2023-09-01 11:57:37 +00:00
Tapani Pälli 48a41c7700 ci: add a fix for KHR-GLES3.packed_pixels.*snorm tests 
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Acked-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24600>
 2023-09-01 10:37:43 +00:00
Tapani Pälli ff17766fbb mesa: remove GL_UNSIGNED_BYTE as supported for snorm reads 
UNSIGNED_BYTE should not be allowed for reading snorm color buffers.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9718
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24600>
 2023-09-01 10:37:43 +00:00
Vlad Schiller 05179931af pvr: Implement VK_EXT_tooling_info 
This commit will enable the EXT_tooling_info extension,
which was already implemented in the common code.

Signed-off-by: Vlad Schiller <vlad-radu.schiller@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24928>
 2023-09-01 10:10:42 +00:00
Rohan Garg 51bee677b3 anv: use the pre defined _3DPRIMITIVE_DIRECT macro 
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24978>
 2023-09-01 08:07:54 +00:00
Konstantin Seurer 0385dcac5c aco/lower_to_cssa: Fix typo 
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24906>
 2023-09-01 07:23:33 +00:00
Konstantin Seurer ce4c38ecae radv: Only generate debug info if required 
Fixes: 51f2fa1a5e ("radv: Break up radv_shader_nir_to_asm")
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24906>
 2023-09-01 07:23:33 +00:00
Konstantin Seurer 2a5d8d4cf4 aco: Unify demote and demote_if selection 
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24906>
 2023-09-01 07:23:33 +00:00
Konstantin Seurer 9af91edda9 aco: Use bytes() instead of size() in emit_wqm 
This should get most of the cases that would fail validation.

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24906>
 2023-09-01 07:23:33 +00:00
Konstantin Seurer 1ddf8378cb aco/validate: Handle p_wqm like p_parallelcopy 
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24906>
 2023-09-01 07:23:32 +00:00
Samuel Pitoiset e104718c9f aco: allow separate compilation of NGG shaders 
Also prevent to emit a long-jump for VS as NGG without a GS.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24907>
 2023-09-01 06:52:40 +00:00
Samuel Pitoiset ee8ba0f98f aco: adjust fix_exports() for VS/TES as NGG and non-monolithic shaders 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24907>
 2023-09-01 06:52:40 +00:00
Samuel Pitoiset bfb39031f1 aco: flag blocks with long-jump as export_end for separate compilation 
This will allow us to adjust fix_exports().

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24907>
 2023-09-01 06:52:40 +00:00
Samuel Pitoiset 05185e8412 radv: preserve shader argument for separate compilation of NGG shaders 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24907>
 2023-09-01 06:52:40 +00:00
Qiang Yu 1f3858509c radeonsi: enable aco compile for part mode standalone vs 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24713>
 2023-09-01 04:44:32 +00:00
Qiang Yu 287f7a9c35 radeonsi: set vs has prolog aco shader info 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24713>
 2023-09-01 04:44:32 +00:00
Qiang Yu 4247b742ec radeonsi: add vs prolog aco build 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24713>
 2023-09-01 04:44:32 +00:00
Qiang Yu 8c3b5ce0c4 radeonsi: fix aco options has_ls_vgpr_init_bug setup 
Fixes: b313d950e2 ("radeonsi: enable aco compile for mono merged LS/HS")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24713>
 2023-09-01 04:44:32 +00:00
Qiang Yu ec57236824 radeonsi: extract si_get_vs_prolog_args to be shared with aco 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24713>
 2023-09-01 04:44:32 +00:00
Qiang Yu 07b62af810 radeonsi: remove is_monolithic from vs prolog key 
We do not generate vs prolog for monolithic shader any more.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24713>
 2023-09-01 04:44:32 +00:00
Dave Airlie b5d9c4ef4f nvk: add build_id linker argument. 
the build id was failing for a gentoo build causing instance
creation to fail, this seems to fix it.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24916>
 2023-09-01 04:00:13 +00:00
Qiang Yu 4c10bf1e6d radeonsi: fill aco_shader_info->is_monolithic 
Fixes: 80177e0296 ("aco: add support for compiling VS+TCS separately on GFX9+")

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24944>
 2023-09-01 03:06:03 +00:00
Karol Herbst 667375999c rusticl/event: disable profiling for devices without timestamps 
Timestamp queries are strictly required, but a bit odd to not expose CL
for not supporting it...

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24938>
 2023-09-01 02:48:55 +00:00
Karol Herbst 8e4d51aa1f rusticl/query: fix use-after-free, but also fix incorrect usage of unsafe 
`PipeQuery::new` create a `PipeQuery` wrapper before handling errors, so
we ended up calling `drop` and destroy_query, meaning the latter ended up
being called twice.

While at it, also restrict visibility of related methods and add some
unsafe declarations.

Fixes: 52e53938c3 ("rusticl: Wrap pipe queries")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24938>
 2023-09-01 02:48:55 +00:00
Lina Versace 6d3a7c1773 docs: Add row for VK_KHR_maintenance5 
Reviewed-By: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24980>
 2023-09-01 01:36:55 +00:00
Matt Turner 01f5fd36c8 intel: Only build perf if drivers or tools are enabled 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24974>
 2023-08-31 21:53:19 +00:00
Matt Turner ce7d41bbc5 intel: Only build ds if drivers are enabled 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24974>
 2023-08-31 21:53:19 +00:00