49a867f67e
intel/fs: Add support for vector payload values to fetch_payload_reg().
...
This extends fetch_payload_reg() to support fetching vector registers
like barycentrics stored on the payload as a contiguous sequence of
SIMD-wide vectors. In the SIMD32 case, both halves of the SIMD16
vector registers specified as regs[0] and regs[1] are zipped to
construct a single SIMD32-wide vector.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26606 >
2023-12-28 11:07:03 -08:00
f295494cee
intel/fs/xe2+: Update poly info PS payload for new multi-polygon dispatch format.
...
This includes the render target array index, viewport index, and
front/back facing fields, which are now replicated per pair of
subspans in order to support fixed-layout multi-polygon PS dispatch.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26606 >
2023-12-28 11:07:03 -08:00
4cc9c37bba
intel/fs/xe2+: Update location of sample ID fields in PS payload.
...
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26606 >
2023-12-28 11:07:03 -08:00
a0ae3c0dba
intel/fs/xe2+: Update uses of pixel/sample mask from PS thread payload.
...
Note from Caio: proper handling of brw_sample_mask_reg
will appear in later patches.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26606 >
2023-12-28 11:07:03 -08:00
6dae56cc57
intel/fs/xe2+: Fix for new layout of X/Y pixel coordinates in PS payload.
...
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26606 >
2023-12-28 11:07:03 -08:00
ef6ef7aa8e
intel/fs/xe2+: Implement PS thread payload register offset setup.
...
The PS thread payload format has changed enough in Xe2 that it
probably doesn't make sense to share code with gfx6. See BSpec page
"PS Thread Payload for Normal Dispatch - 512 bit GRF" for the new
format.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26606 >
2023-12-28 11:07:03 -08:00
24e8709d8b
intel/eu/xe2+: Add helpers for constructing registers in 512b units.
...
These are new variants of the existing brw_reg GRF constructors that
take registers numbers in the new 512b units. Mainly useful for
thread payload setup code to use register numbers in a format that
matches the BSpec.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26606 >
2023-12-28 11:07:03 -08:00
753056fb94
meson: use allow_fallback instead of manually listing the deps and what they provide
...
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26834 >
2023-12-28 13:17:25 +00:00
3465e9f352
anv: Assume that imported bos already have flat CCS requirements satisfied
...
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10291
Signed-off-by: José Roberto de Souza <jose.souza@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26711 >
2023-12-27 18:05:04 +00:00
8d0e70f628
anv: Replace anv_bo.vram_only by anv_bo.alloc_flags check
...
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10291
Signed-off-by: José Roberto de Souza <jose.souza@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26711 >
2023-12-27 18:05:04 +00:00
060439bdf0
anv: Add ANV_BO_ALLOC_IMPORTED
...
The next patch will replace anv_bo.is_vram by a anv_bo.alloc_flags
check but to that actually work we can't use ANV_BO_ALLOC_NO_LOCAL_MEM
for imported bos, so here adding it.
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10291
Signed-off-by: José Roberto de Souza <jose.souza@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26711 >
2023-12-27 18:05:04 +00:00
5683c54d8f
driconf: add Witcher3 to Intel XeSS workaround
...
Reviewed-by: Tapani Pälli <tapani.palli@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26818 >
2023-12-27 17:10:19 +00:00
b77b67064e
driconf: add Dying Light 2 to Intel XeSS workaround
...
Reviewed-by: Tapani Pälli <tapani.palli@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26818 >
2023-12-27 17:10:19 +00:00
55c262898a
iris: Skip mi_builder init for indirect draws
...
We only need it for indirect draws.
Improves performance on an i7-12700 and A770:
- Piglit's drawoverhead base case +150.639% +/- 2.86933% (n=15).
- gfxbench5 gl_driver2_off +19.7219% +/- 1.13778% (n=15)
- SPECviewperf2020 catiav5test1 +1.6831% +/- 0.552052% (n=10).
Cc: mesa-stable
Reviewed-by: José Roberto de Souza <jose.souza@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26806 >
2023-12-27 01:25:04 -08:00
d55b5d4af5
iris: Don't search the exec list if BOs have never been added to one
...
Whenever we use a BO in a batch, we need to find its corresponding exec
list entry, either to a) record that it's been used, b) update whether
it's being written, c) check for cross-batch implicit dependencies.
bo->index exists to accelerate these lookups. If a BO is used multiple
times by a batch, bo->index is its location in the list. Because the
field is global, and a BO can in theory be used concurrently by multiple
contexts, we need to double-check whether it's still there. If not, we
fall back to a linear search of all BOs in the list, looking to see if
our index was simply wrong (but presumably right for another context).
However, there's one glaringly obvious case that we missed here. If
bo->index is -1, then it's wrong for /all/ contexts, and in fact implies
that said BO has never been added to any exec list, ever. This is quite
common in fact: a new BO, never been used before, say from the BO cache,
or streaming uploaders, gets used for the first time.
In this case we can simply conclude that it's not in the list and skip
the linear walk through all buffers referenced by the batch.
Improves performance on an i7-12700 and A770:
- SPECviewperf2020 catiav5test1: 72.9214% +/- 0.312735% (n=45)
Cc: mesa-stable
Reviewed-by: José Roberto de Souza <jose.souza@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26806 >
2023-12-27 01:25:00 -08:00
d178334d5c
iris: Initialize bo->index to -1 when importing buffers
...
A value of -1 means that the buffer has never been used in an execbuf
buffer list in any of our contexts. While setting this isn't critical,
doing so will allow us to short-circuit some looping in the next patch.
Cc: mesa-stable
Reviewed-by: José Roberto de Souza <jose.souza@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26806 >
2023-12-27 01:24:35 -08:00
bd32badbb7
iris: Delay main and aux resource creation on import
...
Follow the pattern for initializing aux resource addresses.
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25768 >
2023-12-26 18:40:38 +00:00
5f93f97892
iris: Use common res fields for imported planes
...
Instead of putting the aux plane info in the aux fields, just use the
same iris_resource fields for all planes.
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25768 >
2023-12-26 18:40:38 +00:00
a0f3c0a246
iris: Inline import_aux_info
...
This function is only used once. By inlining it, we can more easily
compare the CCS plane import code with the clear color plane import
code.
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25768 >
2023-12-26 18:40:38 +00:00
81d132d5ea
iris: Use helpers for generic aux plane importing
...
Inline iris_resource_finish_aux_import and reimplement it with the
helper functions for managing resource planes. Provides more testing for
the helper functions and simplifies the code.
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25768 >
2023-12-26 18:40:38 +00:00
733607cc37
iris: Simplify a plane count check in from_handle
...
Instead of checking the plane count in order to finish importing the aux
info, just check the plane index. Planes are added in reverse, so we'll
have the complete number of planes once we reach plane zero.
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25768 >
2023-12-26 18:40:38 +00:00
79222e5884
iris: Simplify get_main_plane_for_plane
...
Dropping the mod_info parameter simplifies a future commit.
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25768 >
2023-12-26 18:40:38 +00:00
d9ba75e2e1
Revert "vk/util: ignore unsupported feature structs"
...
This reverts commit eb5bb5c784https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26813 >
2023-12-25 20:36:34 +00:00
bc9fe6637b
ci: merge debian-rusticl-testing into debian-testing
...
There is really no point anymore having it split out.
Signed-off-by: Karol Herbst <kherbst@redhat.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26807 >
2023-12-25 16:18:41 +00:00
4d6d0a24ed
ci/msvc: Rename vs2019 to msvc
...
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com >
Reviewed-by: Jesse Natalie <jenatali@microsoft.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26736 >
2023-12-24 11:46:43 +00:00
7e8db6aedf
meson: always define {,DRAW_}LLVM_AVAILABLE one way or the other
...
With the usual benefits of `#if` instead of `#ifdef` (mostly the fact
that typos can be build failures instead of silently being interpreted
as if 0).
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3863 >
2023-12-24 10:01:39 +00:00
c05261a7d8
ci/v3dv: add new failures
...
These failures started with eb5bb5c784jasuarez@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26808 >
2023-12-24 00:48:10 +01:00
551924aa87
ci: apply two bugfixes for VKCTS
...
These are needed for RADV.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26798 >
2023-12-22 20:12:39 +00:00
3e46ee61d5
intel/fs/xe2+: Lift CPS dispatch width restrictions on Xe2+.
...
These restrictions don't seem to be applicable anymore, and limiting
to SIMD8 wouldn't work since we're no longer building shaders with
that dispatch width.
[ Francisco: This one-liner change was squashed by Rohan Garg into a
previous version of my patch "Stop building SIMD8 programs", but it
makes more sense as a separate commit -- Formatted as a separate
patch. ]
Reviewed-by: Francisco Jerez <currojerez@riseup.net >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26605 >
2023-12-22 10:37:00 -08:00
84b53e1a54
intel/fs/xe2+: Pass correct dispatch_width to fs_generator for geometry-processing stages.
...
Instead of hard-coding a dispatch_width value which is no longer
correct on Xe2+.
Reviewed-by: Francisco Jerez <currojerez@riseup.net >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26605 >
2023-12-22 10:37:00 -08:00
3f92dde55e
intel/fs/xe2+: Stop building SIMD8 shaders for geometry stages (VS/TCS/TES/GS).
...
They are no longer suppored by the fixed-function hardware.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26605 >
2023-12-22 10:37:00 -08:00
6877916155
intel/fs/xe2+: Stop building SIMD8 fragment shaders.
...
They are no longer suppored by the fixed-function hardware.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26605 >
2023-12-22 10:37:00 -08:00
7397ba61c2
intel/fs/xe2+: Stop building SIMD8 compute-like shaders (CS/BS/TS/MS).
...
SIMD8 kernels are no longer able to utilize the ALUs efficiently,
since they have twice the vector width as previous platforms. However
even though there aren't many reasons to use it, SIMD8 is still
supported by the instruction set technically, and it will still be
used for some SIMD-lowering sequences.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26605 >
2023-12-22 10:37:00 -08:00
69cc72e50a
anv/gfx12: Hook up dual-SIMD8 fragment shader dispatch.
...
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26585 >
2023-12-22 18:05:31 +00:00
4ec54e84da
iris/gfx12: Hook up dual-SIMD8 fragment shader dispatch.
...
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26585 >
2023-12-22 18:05:31 +00:00
ccb5795938
intel/gfx12: Enable SIMD8 dispatch in 3DSTATE_PS for FS multipolygon dispatch.
...
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26585 >
2023-12-22 18:05:31 +00:00
4868408e6e
intel/genxml: Add 3DSTATE_PS definitions needed for dual-SIMD8 dispatch on Gfx12+.
...
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26585 >
2023-12-22 18:05:31 +00:00
1f2c44dc21
intel/compiler: Attempt to build dual-SIMD8 variant of fragment shaders on gfx12+ platforms.
...
Similar to other FS dispatch modes, attempt to build a dual-SIMD8
program if the regular SIMD8 program didn't spill and doubling the
amount of space for varyings doesn't cause us to go over the thread
payload limit. Dual-SIMD8 builds in combination with coarse pixel
shading are currently not handled.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26585 >
2023-12-22 18:05:31 +00:00
261d07f398
intel: Add debug flag for enabling dual-SIMD8 fragment shader dispatch.
...
Note that this option isn't enabled by default yet pending additional
performance evaluation.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26585 >
2023-12-22 18:05:31 +00:00
28aec45eed
intel/fs/gfx12: Implement multi-polygon format of render target array index in PS payload.
...
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26585 >
2023-12-22 18:05:31 +00:00
5b1ab77423
intel/fs/gfx12: Implement multi-polygon format of back/front-facing flag in PS payload.
...
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26585 >
2023-12-22 18:05:31 +00:00
4672fcbc76
intel/fs: Fix PS thread payload setup for depth_w_coef_reg.
...
It's not replicated per SIMD16 half of a SIMD32 thread on the PS
payload. Make fs_visitor::payload::depth_w_coef_reg a scalar rather
than an array.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26585 >
2023-12-22 18:05:31 +00:00
09ea840987
intel/fs: No need to copy null destinations in lower_simd_width.
...
The copy would be discarded immediately. Until now we were relying on
DCE to eliminate these, but it seems like in some cases MOVs into the
null register emitted by lower_simd_width() are never eliminated,
likely because a lower_simd_width() call has been introduced close to
the bottom of optimize() which isn't follow by any additional DCE
passes.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26585 >
2023-12-22 18:05:31 +00:00
5e0760a993
intel/fs/gfx12: Don't consider multipolygon PS to have packed dispatch.
...
This fixes a number of regressions and hangs in multipolygon fragment
shaders that have FIND_LIVE_CHANNEL sequences which would otherwise
lead to access of a dead channel. Note that the failures don't seem
to be reproducible in simulation.
Acked-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26585 >
2023-12-22 18:05:31 +00:00
8f92baa5d3
intel/fs/gfx12+: Don't set nir_divergence_single_prim_per_subgroup option for fragment shaders.
...
Flat-shaded inputs and other per-primitive values can no longer be
considered to be uniform across fragment shader subgroups due to
multipolygon dispatch.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26585 >
2023-12-22 18:05:31 +00:00
6bf99e6a45
intel/compiler: Don't change types for copies from ATTR file.
...
Since the <8;8,0> regions they use in multipolygon mode could violate
regioning restrictions in some cases, depending on the execution type
of the instruction. Note that the assertion is removed from
try_copy_propagate() since a more accurate check is used within that
function than what fs_inst::can_change_types() can do.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26585 >
2023-12-22 18:05:31 +00:00
2ed36050fb
intel/fs: Don't copy-propagate ATTR registers in multi-polygon FS shaders when invalid.
...
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26585 >
2023-12-22 18:05:31 +00:00
3f89fa63e6
intel/compiler: Pass max_polygons to copy-prop from fs_visitor.
...
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com >
Reviewed-by: Francisco Jerez <currojerez@riseup.net >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26585 >
2023-12-22 18:05:31 +00:00
b62ad4e028
intel/fs: Rework layout of FS vertex setup data in ATTR file to support multi-polygon dispatch.
...
The updated layout includes one copy of each plane parameter per
channel of the SIMD thread, in order to allow channels to process
different polygons.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26585 >
2023-12-22 18:05:31 +00:00
a844c0b185
intel/fs: Fix fs_reg::component_size() to handle two-dimensional register regions.
...
Add code to calculate the size in bytes of arbitrary two-dimensional
regions for FIXED_GRF and ARF registers.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26585 >
2023-12-22 18:05:31 +00:00
Francisco Jerez