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Erik Faye-Lund 437ed05708 compiler/glsl: do not cast struct to string 
When formatting the error here, we're currently casting an
ast_type_qualifier as a string.

But we don't need to use a string here at all, because we know from
context exactly what qualifier we're talking about, because the
if-statements explicitly check for the uniform-qualifier.

So let's just hard-code the format-string to reference the right
qualifier instead of the string-shenanigans. The latter cannot do the
right thing.

Fixes: 2d03f48a65 ("glsl: Add parsing for GLSL uniform blocks.")
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9911>
 2021-04-13 06:16:41 +00:00
Erik Faye-Lund 2a984da18e compiler/glsl: drop rogue argument to _mesa_glsl_error 
This arugment is not present int the format-string, so we shouldn't pass
it to _mesa_glsl_error either.

Noticed by Coverity.

Fixes: 02dc74fbd7 ("glsl: parse invocations layout qualifier for ARB_gpu_shader5")
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9911>
 2021-04-13 06:16:41 +00:00
Marek Olšák a0718e8977 st/mesa: fix nir_lower_io if it's done right after IO vectorization 
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9050>
 2021-04-13 05:07:42 +00:00
Marek Olšák d7250b0b08 gallium: add PIPE_SHADER_CAP_FP16_CONST_BUFFERS for FP16 uniforms 
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9050>
 2021-04-13 05:07:42 +00:00
Marek Olšák b19a836413 glsl: lower mediump uniforms to FP16 based on an option 
Everything else is done - just allow it.

v2: update lower_precision_test.py

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> (v1)
Reviewed-by: Eric Anholt <eric@anholt.net> (v1)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9050>
 2021-04-13 05:07:42 +00:00
Marek Olšák 43270e24b9 mesa: implement glGetActiveUniform for FP16 uniforms 
We must return the types before lowering to 16 bits.

Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9050>
 2021-04-13 05:07:42 +00:00
Marek Olšák d6f3ca95b3 mesa: implement glGetUniform for FP16 uniforms 
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9050>
 2021-04-13 05:07:42 +00:00
Marek Olšák 6bf18fe036 mesa: implement glUniform for packed FP16 uniforms 
Let's just say that this passes dEQP.

If you think the  _mesa_float_to_half conversions are costly, you can
enable FP16 uniforms only if the CPU supports F16C, which is fast.
Drivers will control whether this is used, not common code.

ARM will need something that is equivalent to F16C.

Acked-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9050>
 2021-04-13 05:07:42 +00:00
Marek Olšák 6604aa2606 glsl: pack 16-bit uniforms in the NIR linker 
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9050>
 2021-04-13 05:07:42 +00:00
Alyssa Rosenzweig 5d32cf642f nir: Add varying precision linking helper (v2) 
It is useful for the precisions of varyings to match across shader
stages at link-time to enable precision lowering optimizations, which
would otherwise require costly draw-time fixups.

The goal is to enable `producer->precision == consumer->precision` to be
an invariant drivers may rely on for linked shaders.

v2: keep transform feedback outputs at mediump - mareko

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> (v1)
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9050>
 2021-04-13 05:07:42 +00:00
Marek Olšák fb29cef8dd nir: add many passes that lower and optimize 16-bit input/outputs and samplers 
Added:
* a pass that renumbers bases of IO intrinsics
* a pass that converts mediump IO to 16 bits, optionally using the new
  packed varying slots
* a pass that sets (forces) mediump in IO intrinsics (for testing)
* a pass that remaps VARYING_SLOT_VAR[0..15]_16BIT to VARYING_SLOT_VAR[0..31]
  (if some shader stages don't want packed varyings)
* a pass that folds type conversions around texture opcodes into those
  opcodes (e.g. tex(f2f32(coord), ..) is changed into tex accepting f16)
* a pass that changes (legalizes) sampler src and dst types based on specified
  hw constraints (e.g. derivatives must be the same type as coordinates)

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9050>
 2021-04-13 05:07:42 +00:00
Marek Olšák 73f532e5bf nir: add new VARYING_SLOTs and shader info for packed 16-bit varyings 
This allows mediump inputs and outputs to be trivially lowered into packed
16-bit varyings where 1 slot is occupied by 2 16-bit vec4s, without any
packing instructions in NIR and without any conflicts with 32-bit varyings.

The only thing that is changed is IO semantics in intrinsics to get packed
16-bit varyings.

This simplifies supporting 16-bit types for drivers that have 32-bit slots
everywhere except the fragment shader where they can do 16-bit interpolation
on either the low or high half of each slot.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9050>
 2021-04-13 05:07:42 +00:00
Marek Olšák 5f7c7c9a7f nir: add src and dest types to all IO loads and stores for mediump 
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9050>
 2021-04-13 05:07:42 +00:00
Marek Olšák e06cbff50e compiler: move TEXTURE_COORD/VERTEX_GENERIC_ATTRIB limits into shader_enums.h 
because they are used there.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9050>
 2021-04-13 05:07:42 +00:00
Jesse Natalie 4b69ae8e1e nir_opt_deref: ptr_as_array(deref_cast<T*>(x))[0] isn't the same as x[0] if the cast has alignment 
This breaks CLOn12's handling of CL CTS test_basic vector_creation for char3 (at least).
Removing this cast causes us to try to load from a deref with no alignment info.

Fixes: 99bb2a4d ("nir/opt_deref: Don't remove casts with alignment information")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10165>
 2021-04-13 03:40:23 +00:00
Jesse Natalie 70aefe3449 vtn: Support scoped control barriers for OpenCL too 
The current handling for SPIR-V memory semantics is very specific to
the wording in the SPIR-V spec, which breaks its handling of OpenCL
(compared to what we had working downstream before merging upstream).

Update/relax the logic here to support CL's barrier(CLK_GLOBAL_MEM_FENCE);

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10165>
 2021-04-13 03:40:23 +00:00
Marek Olšák f9b527a9a5 radeonsi: unify internal compute with SSBOs in si_launch_grid_internal_ssbos 
just deduplicate the code

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
 2021-04-13 03:17:42 +00:00
Marek Olšák ec60526035 radeonsi: move binding the internal compute shader into si_launch_grid_internal 
instead of doing it in each function

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
 2021-04-13 03:17:42 +00:00
Marek Olšák aa8a6e5f26 radeonsi: enable DCC for MSAA 4x and 8x on gfx9 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
 2021-04-13 03:17:42 +00:00
Marek Olšák 3120113ee7 radeonsi: implement DCC MSAA 4x/8x fast clear using DCC equations on gfx9 
MSAA 4x and 8x should only clear the first 2 samples because other samples
are uncompressed. The compute shader only clears that subset of DCC.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
 2021-04-13 03:17:42 +00:00
Marek Olšák 8b95f51ef1 radeonsi: fix and enable full DCC with MSAA 2x on gfx9 
This enables fast clear with any clear color (not just 0/1) for bpp >= 32.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
 2021-04-13 03:17:42 +00:00
Marek Olšák 7e68fae25f ac,radeonsi: rewrite DCC retiling without the DCC retile map 
The retile map is removed and replaced by direct DCC address computations
in the retile shader using the new function ac_nir_dcc_addr_from_coord.

The RADV code is disabled.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
 2021-04-13 03:17:42 +00:00
Marek Olšák 35adf91de7 ac/surface: limit the number of swizzle modes that can have displayable DCC 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
 2021-04-13 03:17:42 +00:00
Marek Olšák 5ce8c440dd ac/surface: add a test of DccAddrFromCoord prototype outside of addrlib 
The test takes over 2 minutes on a 12C/24T CPU with OpenMP.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
 2021-04-13 03:17:42 +00:00
Marek Olšák cd2832ee51 meson: add an optional OpenMP dependency for AMD tests 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
 2021-04-13 03:17:42 +00:00
Marek Olšák df2cbdd2e3 amd/addrlib: expose DCC address equations to drivers 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
 2021-04-13 03:17:42 +00:00
Marek Olšák 8771d45a74 ac/surface/tests: fix a random segfault in the modifier test 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
 2021-04-13 03:17:42 +00:00
Marek Olšák 23b2cf032a ac/surface/tests: test Sienna Cichlid and Navy Flounder 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
 2021-04-13 03:17:42 +00:00
Marek Olšák 1b3dbde3b9 ac/surface: only apply the 3D swizzle mode tuning to gfx10+ 
This fixes an addrlib failure on gfx9.

Fixes: b43f40166c "ac/surface: select best swizzle mode for 3D sampler performance"

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
 2021-04-13 03:17:42 +00:00
Marek Olšák ec42f52013 radeonsi: allow DCC_DECOMPRESS via CB with MSAA textures 
The shader-based codepath doesn't support it.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
 2021-04-13 03:17:42 +00:00
Marek Olšák 8277732358 radeonsi: try to fix DCC coherency issues with DCC decompression 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
 2021-04-13 03:17:42 +00:00
Marek Olšák f7c58559f5 radeonsi: refine fast clears for small buffers, always use them for large HTILE 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
 2021-04-13 03:17:42 +00:00
Marek Olšák 06b6af596c radeonsi: do Z-only or S-only HTILE clear using a compute shader doing RMW 
This adds a clear_buffer compute shader that does read-modify-write to
update a subset of bits in HTILE.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
 2021-04-13 03:17:42 +00:00
Marek Olšák 84fa21a611 radeonsi: when transitioning to TC-compat HTILE, try to do a proper clear 
instead of always clearing to uncompressed.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
 2021-04-13 03:17:42 +00:00
Marek Olšák 558ab3310d radeonsi: enable DCC fast clears for non-zero mipmap levels and 0/1 clear values 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
 2021-04-13 03:17:42 +00:00
Marek Olšák 9defe8aca9 radeonsi: implement fast Z/S clears using clear_buffer on HTILE 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
 2021-04-13 03:17:42 +00:00
Marek Olšák e2714d5dd4 radeonsi: indent the code for TC-compatibility HTILE transition 
So that HTILE clears can be nicely inserted into a new else statement there.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
 2021-04-13 03:17:42 +00:00
Marek Olšák fcd01ad444 radeonsi: add si_can_fast_clear_depth/stencil helpers 
for later use

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
 2021-04-13 03:17:42 +00:00
Marek Olšák 4dd8d58ad5 radeonsi: clean up some mess around htile_stencil_disabled 
Set the final value in si_texture_create_object, so that other places
don't have to derive it redundantly.

The only thing to remember is that HTILE stencil can be enabled when
stencil is not present, and it can be disabled when stencil is present
due to various workarounds.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
 2021-04-13 03:17:42 +00:00
Marek Olšák bcd1a69f79 radeonsi: parallelize Z/S conversion into TC-compatible with fast color clears 
It's not really a fast clear, but it's the next logical step towards doing
HTILE clears here.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
 2021-04-13 03:17:42 +00:00
Marek Olšák fb72d41b18 radeonsi: implement Z/S fast clear for non-zero mipmap levels 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
 2021-04-13 03:17:42 +00:00
Marek Olšák 6434b0b652 radeonsi: implement per-level DCC and CMASK fast clears for gfx10+ 
Fast clears are only used for level 0. This enables clearing level 0
of CMASK and DCC on gfx10+ when there are multiple mipmap levels.
vi_dcc_clear_level can also clear any level now.

Mipmapped array textures are still cleared slowly.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
 2021-04-13 03:17:42 +00:00
Marek Olšák 059f042fb1 radeonsi: allow trivial DCC clears for shared textures with DCC constant encode 
This relaxes the existing restriction.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
 2021-04-13 03:17:42 +00:00
Marek Olšák c00b314ae4 radeonsi: restructure DCC disablement into a switch 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
 2021-04-13 03:17:42 +00:00
Marek Olšák fa43d61953 radeonsi: don't cache FMASK transactions from CB in L2 
FMASK is usually pretty large. It's better to leave the cache to shaders.
FMASK stores are still cached, but they can be evicted sooner, which is
the same as other color stores. Only DCC, HTILE, and CMASK are cached.

I haven't benchmarked this, but it seems like the right thing to do.
This only affected APUs.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
 2021-04-13 03:17:42 +00:00
Nanley Chery bc1f715076 iris: Support I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC 
With a resolution of 1600x1200, I measured FPS increases in:

* glxgears 18.04% +/- 0.65% (n=691)
* Nexuiz    3.58% +/- 0.09% (n=553)

compared to the master branch at commit
3f614c6f7c.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9230>
 2021-04-13 02:53:11 +00:00
Nanley Chery 4785aad6a0 iris: Support RC_CCS_CC modifier in plane queries 
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9230>
 2021-04-13 02:53:11 +00:00
Nanley Chery f02951d727 iris: Support clear color plane imports for RC_CCS_CC 
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9230>
 2021-04-13 02:53:11 +00:00
Nanley Chery 11a0584c48 isl: Describe I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC 
v2. Simplify the diff. (Jason)

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9230>
 2021-04-13 02:53:11 +00:00
Nanley Chery 7a69942d29 drm-uapi: Update drm_fourcc.h for new TGL modifier 
Pull in the header from drm-next commit
32c3d9b0f51ee1e6bb0160496b97e50b5caca4d0. Among other things, this
brings in the I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC modifier.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9230>
 2021-04-13 02:53:11 +00:00