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Author SHA1 Message Date
Mike Blumenkrantz a5bd2b95ef zink: optimize renderpass hash table 
only the existing render targets need to be used for table entries

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8487>
 2021-01-14 17:20:03 +00:00
Mike Blumenkrantz 184bbef33d util/set: split off create() into an init() function 
this brings parity with the matching hash_table api

Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8450>
 2021-01-14 13:51:35 +00:00
Mike Blumenkrantz 491e7decad util/set: add the found param to search_or_add 
this brings parity with the internal api

Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8450>
 2021-01-14 13:51:35 +00:00
Mike Blumenkrantz 5f3f128088 util/set: optimize rehash for empty table and no-func clears 
if the table is filled with deleted entries, we don't need to rzalloc+free an identical
block of memory for the table, we can just memset the existing one

the same applies to table clears without a function passed in that the table
doesn't need to be iterated and can just be memset

Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8450>
 2021-01-14 13:51:35 +00:00
Mike Blumenkrantz 41042f7fa2 util/hash_table: optimize rehash for empty table and no-func clears 
if the table is filled with deleted entries, we don't need to rzalloc+free an identical
block of memory for the table, we can just memset the existing one

the same applies to table clears without a function passed in that the table
doesn't need to be iterated and can just be memset

Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8450>
 2021-01-14 13:51:35 +00:00
Pierre-Eric Pelloux-Prayer 17f8e56c96 radeonsi: invalidate compute sgprs in si_rebind_buffer 
If we don't tag compute sgpr as dirty they will point to the
ol buffer location.
This fixes arb_compute_shader-dlist with mcbp enabled.

Fixes: 85a6bcca61 ("radeonsi: pass at most 3 images and/or shader buffers via user SGPRs for compute")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8433>
 2021-01-14 10:33:10 +01:00
Pierre-Eric Pelloux-Prayer c4b7a0d61d ac: add ifdef __cplusplus guard to header 
ac_shadowed_regs.h can be included from si_state_draw.cpp so this commit
adds the needed guards.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8433>
 2021-01-14 10:33:10 +01:00
Michel Dänzer b83d0b2f5d ci: Use meson test directly instead of ninja test 
The former allows specifying how many processes to spawn for tests. The
latter seems to spawn (up to) as many test processes as there are CPU
cores.

Acked-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8451>
 2021-01-14 08:22:30 +00:00
Michel Dänzer 5eb9c6203c ci: Remove .gitlab-ci/meson-build.bat 
Unused since 07885cbcdb "CI: Add native Windows VS2019 build"

Acked-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8451>
 2021-01-14 08:22:30 +00:00
Lionel Landwerlin d4b4d69d4d anv: add transfer usage for color/depth/stencil attachments 
We sometimes use anv_layout_to_aux_state() to compute the aux state of
an image during the resolve operations at the end of a render
(sub)pass.

If we're dealing with a multisampled image that is created without a
transfer usage, our internal code might trigger a resolve using the
transfer layout (see genX_cmd_buffer.c:cmd_buffer_end_subpass), for
which the image doesn't the usage bit. The current code tries to AND
the 2 usages which won't have any bit in common, thus skipping all
checks below.

v2: Add the transfer usages depending on attachment usage (Lionel)

v3: Limit to samples > 1 (Jason) && DEPTH_STENCIL_ATTACHMENT_BIT (Lionel)

v4: Add transfer usage at image creation (Jason)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 54b525caf0 ("anv: Rework anv_layout_to_aux_state")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4037
Reviewed-by: Reviewed-by: Tapani Pälli <tapani.palli@intel.com> (v1)
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8307>
 2021-01-14 09:51:31 +02:00
Danylo Piliaiev ad098553ee turnip/ir3: handle image load/stores produced by AtomicLoad/Store 
SpvOpAtomicLoad and SpvOpAtomicStore are translated into
nir_intrinsic_image_deref_store/load instead of some separate
atomic intrinsics, however they don't have src or dest type
specified. Turnip doesn't support shaderImageFloat32Atomics
so type is just integer.

Fixes:
dEQP-VK.memory_model.message_passing.core11.u32.coherent.fence_fence.atomicwrite.device.payload_local.image.guard_local.image.frag
dEQP-VK.memory_model.message_passing.core11.u32.coherent.fence_fence.atomicwrite.workgroup.payload_local.buffer.guard_local.image.comp
dEQP-VK.memory_model.write_after_read.core11.u32.coherent.fence_fence.atomicwrite.device.payload_local.buffer.guard_local.image.comp
dEQP-VK.memory_model.write_after_read.core11.u32.coherent.fence_fence.atomicwrite.workgroup.payload_local.image.guard_local.image.comp
dEQP-VK.memory_model.write_after_read.core11.u32.coherent.fence_fence.atomicwrite.workgroup.payload_nonlocal.workgroup.guard_local.image.comp

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8476>
 2021-01-14 05:43:56 +00:00
Witold Baryluk 9c54928f77 lavapipe: Defer lavapipe warning to CreateDevice 
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4055
Fixes: b38879f8c5
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8377>
 2021-01-14 01:41:22 +00:00
Vinson Lee aa3dfcd803 panfrost: Fix typos. 
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8400>
 2021-01-14 01:17:55 +00:00
Eric Anholt 179e549995 gallium/tgsi: garbage collect unused TGSI_UTIL_SIGN_MODE. 
Noticed while git grepping for abs/neg stuff.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8369>
 2021-01-13 22:52:10 +00:00
Eric Anholt f44212067e gallium/tgsi: Rewrite the docs on source modifiers. 
Clarify what the rules are, and warn about the exceptions.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8369>
 2021-01-13 22:52:10 +00:00
Eric Anholt 1fc79592b7 gallium/tgsi: Remove support for f64 src modifiers. 
The tgsi.rst was not very clear but didn't indicate that they were
supported, and llvmpipe only supported double abs and not negate.
glsl_to_tgsi never generated them, and neither did the new nir_to_tgsi, so
just garbage collect it.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8369>
 2021-01-13 22:52:10 +00:00
Eric Anholt 9a2cbe02ed gallium/tgsi: Assert that we don't see integer abs modifiers. 
tgsi.rst says it's not supported, and llvmpipe, r600, and virgl don't
support it.  Make sure nobody else introduces them like I did while
testing only on softpipe.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8369>
 2021-01-13 22:52:10 +00:00
Eric Anholt 1ff2c01741 gallium/ntt: Stop lowering integer source mods. 
While tgsi_exec.c (softpipe) implemented 32b integer src mods, the
tgsi.rst documentation says only 32b negate is supported and not abs.
llvmpipe implemented 32 and 64 negate but not abs, virgl implemented
negate incorrectly, and r600 apparently doesn't do any integer src mods.
glsl_to_tgsi has apparently never generated integer src mods.

Given that r600 can't do any integer src mods, just stop trying to
generate them for TGSI.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8369>
 2021-01-13 22:52:10 +00:00
Eric Anholt ecaa7c3e39 gallium/ttn: Add support for TGSI_OPCODE_I64NEG/ABS. 
Found when converting AMD's built-in TGSI shaders to not using 64-bit src
mods.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8369>
 2021-01-13 22:52:10 +00:00
Ilia Mirkin 8c7526afd2 nv50,nvc0: explicitly list recently-added caps 
Some of these should be implemented, but that can be done in a later
change.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8461>
 2021-01-13 17:19:32 -05:00
Ilia Mirkin be7e12d81b nv50/ir: ignore FS_BLEND_EQUATION_ADVANCED 
It's unsupported, but gets set unconditionally by the state tracker,
even when fbfetch is to be used.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8461>
 2021-01-13 17:19:19 -05:00
Mike Blumenkrantz 9d651d2a0f zink: clamp sampler+samplerview limits 
* struct shader_info provides a 32bit mask for textures_used
* samplers and samplerviews are a 1:1 mapping for shader descriptors
* also according to spec this is always 32 per stage

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8457>
 2021-01-13 21:53:56 +00:00
Jason Ekstrand f4902bb189 intel/genxml,anv,iris: Drop the legacy compute path from gen125.xml 
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8342>
 2021-01-13 13:10:28 -08:00
Jordan Justen 32857a6350 iris: Add support for COMPUTE_WALKER 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8342>
 2021-01-13 13:10:28 -08:00
Jason Ekstrand 8f85e68dea anv: Enable push constants on gen12-hp 
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8342>
 2021-01-13 13:10:28 -08:00
Jason Ekstrand 369eab9420 intel/fs: Emit code for Gen12-HP indirect compute data 
Reworks:
 * Jordan: Apply to gen > 12
 * Jordan: Adjust comment about loading constants

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8342>
 2021-01-13 13:10:28 -08:00
Jason Ekstrand 4077ca1cc8 anv: Add a general state pool 
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8342>
 2021-01-13 13:10:28 -08:00
Jordan Justen a6f8d59142 anv: Use COMPUTE_WALKER for gen12-hp 
Rework: Rafael Antognolli, Jason Ekstrand
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8342>
 2021-01-13 13:10:28 -08:00
Jordan Justen 91fe96cfbe anv: Don't use MEDIA_INTERFACE_DESCRIPTOR_LOAD for gen12-hp 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8342>
 2021-01-13 13:10:27 -08:00
Jordan Justen 435b272241 anv: Emit CFE_STATE for gen12-hp 
Rework:
 * make scratch TODO. (Jason)
 * emit_compute_cs_state => emit_compute_state. (Jason)

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8342>
 2021-01-13 13:10:27 -08:00
Jason Ekstrand b4ffbf1521 intel/fs: Allow compute dispatch without a pushed subgroup ID on Gen12-HP 
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8342>
 2021-01-13 13:10:27 -08:00
Jordan Justen 9294193098 intel/compiler: Disable push constants on gen12-hp 
We currently don't use push constants with the COMPUTE_WALKER command.
Make all uniforms to be pull constants.

The local group id previously was a push constant, but is now
available in R0.2[7:0].

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8342>
 2021-01-13 13:10:27 -08:00
Jason Ekstrand b7c1ad00fc intel/tools: Decode COMPUTE_WALKER 
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8342>
 2021-01-13 13:10:27 -08:00
Jordan Justen cdc9e22a3a intel/genxml/gen125: Add CFE_STATE and COMPUTE_WALKER 
Reworks:
 * Jason: Captalize COMPUTE_WALKER::BTD mode
 * Jason: Make COMPUTE_WALKER::InlineData an array
 * Jason: Remove stale fields, uint=>bool, add missing enum values.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8342>
 2021-01-13 13:10:27 -08:00
Dylan Baker 9149d71bb6 docs: update calendar for 21.0.0-rc1 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8478>
 2021-01-13 20:25:25 +00:00
Dylan Baker 68b1e7b234 docs: update calendar and link releases notes for 20.3.3 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8478>
 2021-01-13 20:25:25 +00:00
Dylan Baker 60ffde5994 docs: Add sha256sum for 20.3.3 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8478>
 2021-01-13 20:25:25 +00:00
Dylan Baker 1a20041361 docs: add release notes for 20.3.3 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8478>
 2021-01-13 20:25:25 +00:00
Boris Brezillon 86101cdad7 panfrost: Don't skip the test with a 4k shader 
Commit bfcdc8f174 ("pan/bi: Add some zero bytes after shaders on
Bifrost") should have fixed the problem.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8470>
 2021-01-13 19:17:33 +00:00
Rhys Perry dfe429eb41 nir/loop_unroll: unroll more aggressively if it can improve load scheduling 
Significantly improves performance of a Control compute shader. Also seems
to increase FPS at the very start of the game by ~5% (RX 580, 1080p,
medium settings, no MSAA).

fossil-db (Sienna):
Totals from 81 (0.06% of 139391) affected shaders:
SGPRs: 3848 -> 4362 (+13.36%); split: -0.99%, +14.35%
VGPRs: 4132 -> 4648 (+12.49%)
CodeSize: 275532 -> 659188 (+139.24%)
MaxWaves: 986 -> 906 (-8.11%)
Instrs: 54422 -> 126865 (+133.11%)
Cycles: 1057240 -> 750464 (-29.02%); split: -42.61%, +13.60%
VMEM: 26507 -> 61829 (+133.26%); split: +135.56%, -2.30%
SMEM: 4748 -> 5895 (+24.16%); split: +31.47%, -7.31%
VClause: 1933 -> 6802 (+251.89%); split: -0.72%, +252.61%
SClause: 1179 -> 1810 (+53.52%); split: -3.14%, +56.66%
Branches: 1174 -> 1157 (-1.45%); split: -23.94%, +22.49%
PreVGPRs: 3219 -> 3387 (+5.22%); split: -0.96%, +6.18%

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6538>
 2021-01-13 18:54:18 +00:00
Rob Clark 74748f16c9 freedreno/ir3: Remove legacy packed-struct encoding 
Note that we can't actually remove the packed structs themselves yet,
because tu still uses them in some hand-coded blit shaders.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7997>
 2021-01-13 18:32:48 +00:00
Rob Clark 1a8113fdee freedreno/ir3/decode: Switch over to new disasm 
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7997>
 2021-01-13 18:32:48 +00:00
Rob Clark 668943e9f7 freedreno/ir3: Realign disasm shader stats 
To better match up with what mesa shader-db stats look like, for easier
comparision.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7997>
 2021-01-13 18:32:47 +00:00
Rob Clark 3e15ba5ccc freedreno/ir3: Better sstall estimation 
1) Take into account repeat/nop cycles
2) Clear sfu_delay after an (ss) sync

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7997>
 2021-01-13 18:32:47 +00:00
Rob Clark 11cba228fd freedreno/ir3: Small resinfo disasm tweak 
Add the 'type' field.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7997>
 2021-01-13 18:32:47 +00:00
Rob Clark 5cae4779c2 freedreno/ir3: Switch over to new encoder/decoder 
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7997>
 2021-01-13 18:32:47 +00:00
Rob Clark 01e8bd55de freedreno/ir3/tests: Switch disasm test over to new decoder 
Also, uncomment the `stc` test vectors (since the new decoder decodes
these properly) and comment out an instruction which looks suspiciously
like -6.0 in hex.

This also switches the parser back to `atomic.b.op` from `atomic.op.b`
which was a short-term workaround to make it easier for the legacy
disassembler.

Also switch the binary encoding for ldib to clear b0, because the new
disassembler warns about unexpected dontcare bits (which cases the
disasm to not match).

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7997>
 2021-01-13 18:32:47 +00:00
Rob Clark 704e49bae0 freedreno/hw/isa: Add expression caching 
Drops decoding an ~850KB collection of instructions from ~4min to ~1sec.

Granted for normal sized shaders, this probably doesn't matter.. but it
at reduces my cycle time for fixing things to match existing disasm
syntax using this massive collection of unique instructions.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7997>
 2021-01-13 18:32:47 +00:00
Rob Clark 6d94f575d2 freedreno/hw/isa: Add description of ir3 ISA 
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7997>
 2021-01-13 18:32:47 +00:00
Rob Clark e7630ec278 freedreno/hw: Add isaspec mechanism for documenting/defining an ISA 
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7997>
 2021-01-13 18:32:47 +00:00