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Author SHA1 Message Date
Samuel Pitoiset
344040c367 radv: enable RADV_THREAD_TRACE_CACHE_COUNTERS on GFX12 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38489>
 2025-11-21 11:52:58 +00:00
Samuel Pitoiset
473118b6eb ac/spm: use hardware names for performance counters 
Much easier to read.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38489>
 2025-11-21 11:52:58 +00:00
Samuel Pitoiset
4c21a4846c ac/spm: adjust the granularity of SPM results on GFX12 
It's 1, only GFX11-11.5 uses units of segment.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38489>
 2025-11-21 11:52:58 +00:00
Samuel Pitoiset
f434c5c934 ac/spm: add cache counters configuration for GFX12 
This is for the cache counters prior to RGP 2.6.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38489>
 2025-11-21 11:52:58 +00:00
Samuel Pitoiset
da07f1ef3f radv: allocate the SQTT BO in GTT for faster readback 
Reading VRAM from CPU is very slow.

This is similar to the SPM BO, and generating RGP captures is now
way faster.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38551>
 2025-11-21 11:34:09 +00:00
Valentine Burley
d2ebe7719c ci/android: Build zink for arm64 as well 
We'd like to use zink on both x86_64 and arm64 on Android, so add it to
the build targets.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38572>
 2025-11-21 10:50:43 +01:00
Laura Nao
b10369631e ci/container: Add script to build Perfetto tracebox 
Add a script to build Perfetto’s tracebox tool for x86_64 and arm64
targets on Linux and Android.

Signed-off-by: Laura Nao <laura.nao@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38517>
 2025-11-21 09:59:40 +01:00
Laura Nao
f9243dc92b ci/prepare-artifacts: Keep pps-producer binary in artifacts 
Mesa builds using -Dperfetto=true generate a pps-producer binary.
Include it in the artifacts for use in runtime performance tracing
tests.

Signed-off-by: Laura Nao <laura.nao@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38517>
 2025-11-21 09:59:40 +01:00
Laura Nao
b178612f11 ci: Enable Perfetto tracing support in Mesa builds for Linux/Android 
Enable Perfetto tracing support in Mesa's x86_64/arm64 builds for Linux
and Android. This enables GPU performance counter collection via pps and
sets up the environment for runtime GL tests with support for CPU, GPU
and system-wide tracing. Information captured by Perfetto will provide
driver developers insight into the test environment and help identify
factors affecting performance.

Signed-off-by: Laura Nao <laura.nao@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38517>
 2025-11-21 09:59:40 +01:00
Yiwei Zhang
fcd2acba41 ci/venus: skip Android incremental and shared present tests 
Those are mainly to test platform features, and they take too long. So
we skip.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38568>
 2025-11-20 21:55:38 -08:00
Faith Ekstrand
17b9bc2770 spirv: Only set workgroup_size_variable on compute-like stages 
This should be ignored on non-compute stages but AGX changes 3D shaders
to compute without setting the workgroup size and blows up if it claims
variable workgroups.  The safest thing is to only set it from
spirv_to_nir for stages that actually have workgroups.

Fixes: 6d9f563960 ("spirv: Assume variable workgroup size unless it's set")
LoLed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38555>
 2025-11-20 23:15:28 +00:00
Ryan Houdek
0f2dcf656a freedreno/fdl: Optimize linear_to_tiled with avx2 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38249>
 2025-11-20 22:42:07 +00:00
Kenneth Graunke
3160c516ca brw: Delete input_slots_valid from brw_wm_prog_key 
Nothing in the compiler seems to use this anymore.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38556>
 2025-11-20 14:10:39 -08:00
Kenneth Graunke
868377e4c7 brw: Delete program_string_id from brw program keys 
This is strictly a GL thing.  iris can manage it in its own program keys
without polluting the compiler with stuff nobody else cares about.

We can also drop a lot of padding that was introduced in commit
a18835a9ca which doesn't appear to be
necessary.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38556>
 2025-11-20 14:10:38 -08:00
Kenneth Graunke
fbd9bf6aeb iris: Use iris_any_prog_key, not brw_any_prog_key 
We're storing iris keys here, not brw keys.  This worked because brw
keys are larger so you could fit any iris key in the memory.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38556>
 2025-11-20 14:10:34 -08:00
Matt Turner
ad14942300 meson: Fix sysprof-capture-4 dependency 
The versioning scheme changed in v45.0 (the previous version was
3.48.0). As such, this version check would wrongly accept e.g. 48.0.

Fixes: e9341568fa ("meson: require sysprof-capture-4 >= 4.49.0")
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38557>
 2025-11-20 20:53:36 +00:00
Yurii Kolesnykov
8cc06191a8 apple_cgl.c: Fix error: call to undeclared function 'os_get_option' 
Signed-off-by: Yurii Kolesnykov <root@yurikoles.com>
Fixes: 222b85328e ("mesa: replace most occurrences of getenv() with os_get_option()")
Reviewed-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Mel Henning <mhenning@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38429>
 2025-11-20 18:39:19 +00:00
Yurii Kolesnykov
4913177b14 loader: Wrap nouveau_zink_predicate with HAVE_LIBDRM 
Signed-off-by: Yurii Kolesnykov <root@yurikoles.com>
Fixes: 265afd9bfd ("loader: Don't fall back to nouveau GL without zink")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14290
Reviewed-by: Mel Henning <mhenning@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38429>
 2025-11-20 18:39:19 +00:00
Marek Olšák
d7f03c649e nir/lower_io_passes: only sort variables for nir_lower_io_vars_to_temporaries 
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38470>
 2025-11-20 12:17:31 -05:00
Marek Olšák
02148dc6bc nir/lower_io_passes: fold bool lower_indirect_inputs 
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38470>
 2025-11-20 12:17:30 -05:00
Marek Olšák
9b4fc64324 nir/lower_io_passes: simplify conditions for when to lower IO to temps 
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38470>
 2025-11-20 12:17:28 -05:00
Marek Olšák
edfa3fdfbc nir/lower_io_passes: lower indirect TCS outputs sooner and clarify the behavior 
We don't have to enter the lower-IO-to-temps block for TCS at all.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38470>
 2025-11-20 12:17:26 -05:00
Anna Maniscalco
3e01031f10 radv: consistently use the value in bytes for esgs_itemsize 
Previosuly this value was in bytes for vs/tes and in dwords for gs.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38514>
 2025-11-20 16:45:37 +00:00
Anna Maniscalco
5e8885a339 radv: recalculate legacy_gs_info on bind 
Previously legacy_gs_info calculated based on
gs_info->legacy_gs_info.esgs_itemsize which is calculated based on gs
input varyings.

However, when using ESO vs/tes can have outputs not read by gs, which
leads to underestimating LDS usage.

Cc: mesa-stable
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38514>
 2025-11-20 16:45:37 +00:00
Karmjit Mahil
36f6cf8a35 freedreno/registers: Clarify bit 64B of CP_REG_TO_MEM 
One might think that the `64B` bit might be affecting just the
memory size, but that's not the case as it affects the register
count too. Setting `64B` with `CNT` of `1` actually copies 2
registers, and not 1.

Signed-off-by: Karmjit Mahil <karmjit.mahil@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38535>
 2025-11-20 16:20:43 +00:00
Samuel Pitoiset
9c34567a4a vulkan: stop excluding Shader64BitIndexingEXT SPIR-V cap 
The SPIRV spec has been fixed since
3853dc11e5 ("spirv: Update the JSON and headers").

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38543>
 2025-11-20 15:44:04 +00:00
José Roberto de Souza
334ffcda14 iris: Release global_bufmgr_list_mutex on missing error paths 
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: stable
Reported-by: Taketo Kabe
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13692
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38537>
 2025-11-20 14:24:25 +00:00
Karmjit Mahil
bfdccc7563 freedreno/registers: Mark functions as constexpr where possible 
This makes it possible for these to be used in static_asserts or if
we want to get a register offset (gen agnostic) and have it be
marked as constexpr. E.g.
```
constexpr uint32_t src_reg = __TPL1_A2D_SRC_TEXTURE_BASE<CHIP>({}).reg;
```

Signed-off-by: Karmjit Mahil <karmjit.mahil@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38549>
 2025-11-20 13:56:18 +00:00
Rob Clark
a9c64b737d freedreno: Collapse A6XXProps/A7XXProps 
Now that they are the same thing, simplify the py code a bit.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38515>
 2025-11-20 13:16:11 +00:00
Rob Clark
1574ddffb7 freedreno: Move magic/magic_raw out of props 
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38515>
 2025-11-20 13:16:11 +00:00
Rob Clark
43dd11ca6a freedreno: Flatten fd_dev_info props 
Attempting to separate things out by gen is a bit arbitrary.  And gets
increasingly awkward as we introduce gen8 support, which builds on gen7
but changes some a6xx values.

Just move it all into a single 'props' struct.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38515>
 2025-11-20 13:16:10 +00:00
Rob Clark
062e90f19b freedreno: Move RB_CCU_DBG_ECO_CNTL to raw_magic_regs 
This only needs to be programmed by UMD for a7xx.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38515>
 2025-11-20 13:16:09 +00:00
Rob Clark
231ff1c14d freedreno: Move UCHE_UNKNOWN_0E12 to raw_magic_regs 
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38515>
 2025-11-20 13:16:08 +00:00
Rob Clark
17a6456b84 freedreno: Move VPC_DBG_ECO_CNTL to raw_magic_regs 
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38515>
 2025-11-20 13:16:06 +00:00
Rob Clark
f9d3f6f95c freedreno: Move HLSQ_DBG_ECO_CNTL to raw_magic_regs 
This reg only exists in a6xx.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38515>
 2025-11-20 13:16:05 +00:00
Rob Clark
39cd8d6d24 freedreno: Move SP_DBG_ECO_CNTL to raw_magic_regs 
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38515>
 2025-11-20 13:16:03 +00:00
Rob Clark
1c8b9ad594 freedreno: Move PC_MODE_CNTL to raw_magic_regs 
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38515>
 2025-11-20 13:16:02 +00:00
Rob Clark
d18d75a236 freedreno: Move UCHE_CLIENT_PF to raw_magic_regs 
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38515>
 2025-11-20 13:16:01 +00:00
Rob Clark
bc4bdf58ec freedreno: Move SP_CHICKEN_BITS to raw_magic_regs 
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38515>
 2025-11-20 13:15:59 +00:00
Rob Clark
6d13e0a4cc freedreno: Move GRAS_DBG_ECO_CNTL to raw_magic_regs 
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38515>
 2025-11-20 13:15:58 +00:00
Rob Clark
8f0c920a52 freedreno: Move TPL1_DBG_ECO_CNTL to raw_magic_regs 
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38515>
 2025-11-20 13:15:57 +00:00
Rob Clark
e81defa52d freedreno: Move *_POWER_CNTL to raw_magic_regs 
These two regs only exist in a6xx.  And only need a static value.  So
move them to raw_magic_regs and drop the fd_dev_info field and
corresponding driver code.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38515>
 2025-11-20 13:15:57 +00:00
Michal Krol
31d69602d8 lavapipe: Bump maxGeometryInputComponents to 128. 
D3D11's minimum requirement is 32 GS input registers.

venus: Triage unexpected passes.

Reviewed-by: Brian Paul brian.paul@broadcom.com
Reviewed-by: Roland Scheidegger <roland.scheidegger@broadcom.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38519>
 2025-11-20 11:16:02 +00:00
Pierre-Eric Pelloux-Prayer
bac9d17ead radeonsi/sqtt: clear out sqtt bo on resize 
If the resizing fails, we shouldn't use the destroyed bo anymore.

Fixes: 5794a86f19 ("radeonsi/sqtt: support sqtt buffer auto-resizing")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38529>
 2025-11-20 10:21:47 +00:00
Pierre-Eric Pelloux-Prayer
9e76f5f2a2 radv: enable global BO list if vm_always_valid is supported 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38529>
 2025-11-20 10:21:47 +00:00
Pierre-Eric Pelloux-Prayer
cf4c55a20f ac/info: get vm_always_valid support through ac_linux_drm 
For virtio it depends on the host support in virglrenderer.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38529>
 2025-11-20 10:21:47 +00:00
Pierre-Eric Pelloux-Prayer
f57993b71d ac/virtio: fix incorrect NULL check 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38529>
 2025-11-20 10:21:47 +00:00
Pierre-Eric Pelloux-Prayer
51365585e2 ac/virtio: remove dead code 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38529>
 2025-11-20 10:21:47 +00:00
Samuel Pitoiset
3889695e9f aco/tests: switch to drm-shim 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38536>
 2025-11-20 09:53:29 +00:00
Samuel Pitoiset
a729b0ebaa meson: require drm-shim for ACO tests 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38536>
 2025-11-20 09:53:29 +00:00