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Author SHA1 Message Date
Lionel Landwerlin cb8a878b53 intel: enable protected context creation along with engines 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22898>
 2023-05-08 20:40:20 +00:00
Christopher Snowhill a6d4139e59 Corrects log print to produce hexadecimal base output 
Matching the original %016lx, and the "0x" prefix which is still
in the format string.

Fixes: 53b77a8102 ("anv: remove 48bit address space checks")

Signed-off-by: Christopher Snowhill <kode54@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22882>
 2023-05-07 21:33:18 +00:00
Lionel Landwerlin fb13360546 intel/fs: reduce register usage for relocated constants 
Commit bb8e31b7ed ("anv: avoid hardcoding instruction VA constant in
shaders") had a slight negative impact on shaders (Red Dead Redemption
2 in particular). Dropping a few shaders from SIMD32 to SIMD16.

With this change, it brings back all the dropped SIMD32 shaders.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22872>
 2023-05-07 19:38:04 +00:00
Marcin Ślusarz d6ece34418 intel/tools: decode ACTHD printed by newer kernels 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22874>
 2023-05-05 14:55:41 +00:00
Lionel Landwerlin e64f5f261e anv: increase instruction heap to 2Gb 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8917
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22847>
 2023-05-05 14:48:15 +03:00
Lionel Landwerlin c60e94d61f anv: make internal address space allocation more dynamic 
We're about to manipulate these pools and dealing with the fix address
ranges is painful.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22847>
 2023-05-05 14:48:15 +03:00
Lionel Landwerlin 843afd4c63 anv: link anv_bo to its VMA heap 
We want to add more heaps in the future and so not having to do
address checks to find out in what heap to release a BO is convinient.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22847>
 2023-05-05 14:48:15 +03:00
Lionel Landwerlin bb8e31b7ed anv: avoid hardcoding instruction VA constant in shaders 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22847>
 2023-05-05 14:48:15 +03:00
Lionel Landwerlin 53b77a8102 anv: remove 48bit address space checks 
All the supported platforms should have 36+ bits of virtual address
space.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22847>
 2023-05-05 14:48:15 +03:00
Tapani Pälli c35d430460 isl: fix layout for comparing surf and view properties 
These asserts were checking isl_format_layout against itself, change
to compare surface format layout against view format layout.

Fixes: 628bfaf1c6 ("intel/isl: Add some sanity checks for compressed surfaces")
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22790>
 2023-05-05 08:48:53 +00:00
Lionel Landwerlin 9471ffa70a intel/fs: fix scheduling of HALT instructions 
With the following test :

dEQP-VK.spirv_assembly.instruction.terminate_invocation.terminate.no_out_of_bounds_load

There is a :

shader_start:
   ...                                 <- no control flow
   g0 = some_alu
   g1 = fbl
   g2 = broadcast g3, g1
   g4 = get_buffer_size g2
   ...                                 <- no control flow
   halt                                <- on some lanes
   g5 = send <surface>, g4

eliminate_find_live_channel will remove the fbl/broadcast because it
assumes lane0 is active at get_buffer_size :

shader_start:
   ...                                 <- no control flow
   g0 = some_alu
   g4 = get_buffer_size g0
   ...                                 <- no control flow
   halt                                <- on some lanes
   g5 = send <surface>, g4

But then the instruction scheduler will move the get_buffer_size after
the halt :

shader_start:
   ...                                 <- no control flow
   halt                                <- on some lanes
   g0 = some_alu
   g4 = get_buffer_size g0
   g5 = send <surface>, g4

get_buffer_size pulls the surface index from lane0 in g0 which could
have been turned off by the halt and we end up accessing an invalid
surface handle.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20765>
 2023-05-05 00:43:25 +03:00
Kenneth Graunke 9dd6fcd9ec intel/compiler: UNDEF SubgroupInvocation's register 
This value takes a few instructions to create, involving expanding
V-immediates, adding 8 for SIMD16, and so on.  We can mark it UNDEF
so that it's clear that although these are partial writes, we are
actually defining the entire value.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22835>
 2023-05-04 18:17:26 +00:00
Kenneth Graunke 4913f54a1f intel/compiler: UNDEF comparisons with smaller than 32-bit 
Comparisons which produce 32-bit boolean results (0 or 0xFFFFFFFF)
but operate on 16-bit types would first generate a CMP instruction
with W or HF types, before expanding it out.  This CMP is a partial
write, which leads us to think the register may contain some prior
contents still.  When placed in a loop, this causes its live range
to extend beyond its real life time.

Mark the register with UNDEF first so that we know that no prior
contents exist and need to be preserved.

This affects:
flt32, fge32, feq32, fneu32, ilt32, ult32, ige32, uge32, ieq32, ine32

On one of Cyberpunk 2077's most complex compute shaders, this reduces
the maximum live registers from 696 to 537 (22.8%).  Together with the
next patch, Cyberpunk's spills and fills are cut by 10.23% and 9.19%,
respectively.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22835>
 2023-05-04 18:17:26 +00:00
Lionel Landwerlin f3d648d20d anv: implement VK_KHR_ray_tracing_position_fetch 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <f{merge_request.web_url}>
 2023-05-04 11:25:41 +00:00
Lionel Landwerlin 5cdcc22736 intel/nir/rt: wire position fetch intrinsic 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <f{merge_request.web_url}>
 2023-05-04 11:25:41 +00:00
Lionel Landwerlin 03f0f70adf intel/nir/rt: use a single load for instance leaf loading 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <f{merge_request.web_url}>
 2023-05-04 11:25:41 +00:00
Dave Airlie fa938dd975 vulkan: write beta extensions into generator scripts. 
Updated by: Hyunjun Ko <zzoon@igalia.com>

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21806>
 2023-05-04 02:40:06 +00:00
Lionel Landwerlin 5489033fa8 intel/compiler: make uses_pos_offset a tri-state 
This value depends on the per-sample value which can be unknown at
compile time with graphics pipeline libraries. So we need to have this
dynamic has well and pick the right value when generating the
3DSTATE_PS/3DSTATE_WM packet.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: d8dfd153c5 ("intel/fs: Make per-sample and coarse dispatch tri-state")
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22728>
 2023-05-03 10:03:57 +00:00
Constantine Shablia a252a9dc24 anv: move get_features after get_device_extensions (ugly diff) 
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22333>
 2023-05-03 03:27:54 +00:00
Constantine Shablya 430abb971a anv: switch to using the common vkGetPhysicalDeviceFeatures2 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22333>
 2023-05-03 03:27:54 +00:00
Constantine Shablya 61413d70a0 vulkan: introduce supported_features parameter to vk_physical_device_init 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22333>
 2023-05-03 03:27:54 +00:00
Michel Dänzer 6c7400f4e8 vulkan: Fix GetPhysicalDeviceSparseImageFormatProperties definitions 
To match the declarations (and the corresponding definition in Vulkan
headers).

Pointed out by GCC 13, e.g.:

../src/intel/vulkan_hasvk/anv_formats.c:1589:6: error: conflicting types for 'anv_GetPhysicalDeviceSparseImageFormatProperties' due to enum/integer mismatch; have 'void(struct VkPhysicalDevice_T *, VkFormat,  VkImageType,  uint32_t,  VkImageUsageFlags,  VkImageTiling,  uint32_t *, VkSparseImageFormatProperties *)' {aka 'void(struct VkPhysicalDevice_T *, VkFormat,  VkImageType,  unsigned int,  unsigned int,  VkImageTiling,  unsigned int *, VkSparseImageFormatProperties *)'} [-Werror=enum-int-mismatch]
 1589 | void anv_GetPhysicalDeviceSparseImageFormatProperties(
      |      ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
In file included from ../src/intel/vulkan_hasvk/anv_private.h:113,
                 from ../src/intel/vulkan_hasvk/anv_formats.c:24:
src/intel/vulkan_hasvk/anv_entrypoints.h:120:30: note: previous declaration of 'anv_GetPhysicalDeviceSparseImageFormatProperties' with type 'void(struct VkPhysicalDevice_T *, VkFormat,  VkImageType,  VkSampleCountFlagBits,  VkImageUsageFlags,  VkImageTiling,  uint32_t *, VkSparseImageFormatProperties *)' {aka 'void(struct VkPhysicalDevice_T *, VkFormat,  VkImageType,  VkSampleCountFlagBits,  unsigned int,  VkImageTiling,  unsigned int *, VkSparseImageFormatProperties *)'}
  120 |   VKAPI_ATTR void VKAPI_CALL anv_GetPhysicalDeviceSparseImageFormatProperties(VkPhysicalDevice physicalDevice, VkFormat format, VkImageType type, VkSampleCountFlagBits samples, VkImageUsageFlags usage, VkImageTiling tiling, uint32_t* pPropertyCount, VkSparseImageFormatProperties* pProperties);
      |                              ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22718>
 2023-05-01 14:15:15 +00:00
Felix DeGrood 61c209095c anv: Enable INTEL_DEBUG_BATCH_FRAME_START/_STOP 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22564>
 2023-04-28 04:37:05 +00:00
Felix DeGrood 015eecde47 intel/debug: Control start/stop frame of batch debug 
When using INTEL_DEBUG=bat, INTEL_DEBUG_BATCH_FRAME_START and
INTEL_DEBUG_BATCH_FRAME_STOP can limit dumping of batches for
particular frame ranges. Batch dumps are huge. Smart filtering
allows debugging of single frames during game play. Initial
commit to debug infrastructure.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22564>
 2023-04-28 04:37:05 +00:00
Lionel Landwerlin 7ddc31c672 intel/fs: fix per vertex input clamping 
Only apply the clamp in multi patch mode (where the input vertices
vary between [1, 32]).

The clamp NIR pass operates on lowered intrinsics so we need to call
it after the inputs have been lowered.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: e25e17dd0c ("intel/fs: clamp per vertex input accesses to patchControlPoints")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8912
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22701>
 2023-04-27 20:29:16 +00:00
José Roberto de Souza 65265d3e32 anv: Take into consideration physical device max heap size to set maxStorageBufferRange 
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22721>
 2023-04-27 14:05:42 +00:00
Lionel Landwerlin 5f43f866a2 anv: enable shaderUniformBufferArrayNonUniformIndexing 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22624>
 2023-04-27 09:08:03 +00:00
Lionel Landwerlin 9fb9ae5ac6 anv: fix anv_nir_lower_ubo_loads pass 
In order to use load_global_const_block_intel we need to ensure the
64bit address in src[0] is uniform. This is not the case in the
vkd3d-proton test_bindless_cbv tests for example.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22624>
 2023-04-27 09:08:03 +00:00
Sviatoslav Peleshko 697ed61e7c anv: Improve image/view usage bits verification 
This change makes usage bits verification closer to the Vulkan spec.
i.e. VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT does not always require all formats
to support all the requested usage bits.
Also, VK_IMAGE_CREATE_EXTENDED_USAGE_BIT, when combined with
VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT can relax the requirements for the
usage supported by the original image format.

v2: Removed strict verification of the format_list_info formats usage
    per chadversary's suggestion. Other minor style/comments tweaks.

v3: Added checking of all compatible formats when
    VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT and VK_IMAGE_CREATE_EXTENDED_USAGE_BIT
    are specified, but no list of possible formats was given.

v4: Add VK_IMAGE_CREATE_BLOCK_TEXEL_VIEW_COMPATIBLE_BIT handling.

Cc: 22.2 <mesa-stable>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6031
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17182>
 2023-04-27 01:04:44 +00:00
Sviatoslav Peleshko 9899151361 anv: Handle UNDEFINED format in image format list 
It's not invalid to have this value in the list, but the only case it
is actually valid as format in the creation of an image or image view
is with Android Hardware Buffers which have their format specified
externally.

So we can just ignore all entries with VK_FORMAT_UNDEFINED.

Cc: 22.2 <mesa-stable>
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17182>
 2023-04-27 01:04:44 +00:00
Sviatoslav Peleshko 0ed8a48ce9 isl: Check all channels in isl_formats_have_same_bits_per_channel 
Cc: 22.2 <mesa-stable>
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17182>
 2023-04-27 01:04:44 +00:00
Lionel Landwerlin 5c214117ad intel/tools: add ability to dump out raw kernels data 
Useful for debug.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22703>
 2023-04-26 10:00:54 +00:00
Mark Janes acb2a7d2ec intel/dev: report stepping for TGL systems 
Workaround 14010672564 requires a check for the TGL B0 stepping.

Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22458>
 2023-04-26 02:00:17 +00:00
Mark Janes 47ac056d0f intel/dev: update mesa_defs.json from defect database 
These modifications represent:

 * changes to defects made since Feb 16, 2023
 * changes to automated processing of defect state

Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22458>
 2023-04-26 02:00:17 +00:00
Tapani Pälli e501b31e15 anv: implement state cache invalidate for Wa_16013063087 
Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22651>
 2023-04-25 10:45:55 +00:00
Tapani Pälli 72fc56aa37 anv: cleanup bitmask construction for PIPELINE_SELECT 
Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22651>
 2023-04-25 10:45:55 +00:00
Iván Briano 4cfb4f7d12 anv: support fast color clears on vkCmdClearAttachments 
As long as some conditions are met.

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20175>
 2023-04-24 21:33:49 +00:00
Iván Briano 5faf75dd74 anv: expose some helper functions 
v2: (Rohan Garg)
- Make set_fast_clear_state take an image and format instead of an iview

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20175>
 2023-04-24 21:33:49 +00:00
Iván Briano 9046319cc9 anv: factor out code for ccs_op and mcs_op 
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20175>
 2023-04-24 21:33:49 +00:00
Iván Briano 2a67a1f0c2 anv: make anv_can_fast_clear_color_view more generally available 
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20175>
 2023-04-24 21:33:49 +00:00
Iván Briano a2e02c4ba4 anv: Remove dead parameters from copy_fast_clear_dwords 
There's only one caller of this function and always passes false.

v2: (Nanley Chery)
- Also remove the aspect parameter

v3: (Nanley Chery)
- Rename the function so it's more clear in which direction it works

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20175>
 2023-04-24 21:33:49 +00:00
Sagar Ghuge e488773b29 anv: Fast clear depth/stencil surface in vkCmdClearAttachments 
Instead of doing a slow depth clear, we can do depth fast clear in
vkClearAttachments.

Sascha Willems occlusionquery demo shows more than 2% perf boost with
this series.

On Felix's Tigerlake with the GPU at fixed frequency, this patch
improves performance of RoTR by +0.5%.

v2: (Nanley Chery)
- Clear stencil surface along with depth.
- Check for multilayer resources.
- Lookout for state.attachments.
- Fallback on slow clear for BDW and CHV if conditional rendering
  enabled.
- Keep flush in same function.

v3: (Nanley Chery)
- Return immediately after fast clearing.
- Remove unnecessary comment.

v4: (Nanley Chery)
- Add assertion for BLORP_BATCH_NO_EMIT_DEPTH_STENCIL.
- Remove unnecessary local variable.
- Add 3DSTATE_WM_HZ_OP comment.

v5: (Nanley Chery)
- Fix comments.
- Don't take fast depth clear path if BLORP_BATCH_PREDICATE_ENABLE set.
- Refactor code in can_hiz_clear_att.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20175>
 2023-04-24 21:33:49 +00:00
Sagar Ghuge ee03b30e45 anv: Move and make anv_can_hiz_clear_ds_view non-static 
v2:
- Pass const image view param. (Nanley)

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20175>
 2023-04-24 21:33:49 +00:00
Sagar Ghuge e04a414206 anv: Factor out code from anv_image_hiz_clear 
Refactoring code from anv_image_hiz_clear which helps in future patches
to support fast depth clear in vkCmdClearAttachments.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20175>
 2023-04-24 21:33:48 +00:00
Marcin Ślusarz aa45b13398 anv: move nir_shader_gather_info to anv_pipeline_nir_preprocess 
Fixes dEQP-VK.mesh_shader.ext.misc.custom_attributes*.

Fixes: 16c7c37718 ("anv: move preprocessing of NIR right before compilation")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22629>
 2023-04-24 08:43:51 +00:00
Lionel Landwerlin 56840e4c89 anv: rework Wa_14017076903 to only apply with occlusion queries 
Fixes KHR-GL46.transform_feedback.* tests with zink+anv on DG2

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: c34916f841 ("anv: implement occlusion query related Wa_14017076903")
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22586>
 2023-04-21 12:48:52 +00:00
Jordan Justen fcb72ffd0c intel/compiler/gfx12.5+: Lower 64-bit cluster_broadcast with 32-bit ops 
For MTL (verx10 == 125), float64 is supported, but int64 is not.
Therefore we need to lower cluster broadcast using 32-bit int ops.

For gfx12.5+ platforms that support int64, the register regions
used by cluster broadcast aren't supported by the 64-bit pipeline.

On MTL, dEQP-VK.subgroups.clustered.*_double* and
dEQP-VK.subgroups.clustered.*_dvec* were failing to validate the
compiled shader in debug mode, and reportedly gpu-hanging in release
mode.

With this change dEQP-VK.subgroups.clustered.*_double* passed all 48
tests and dEQP-VK.subgroups.clustered.*_dvec* passed all 140 tests on
MTL.

Rework:
 * Move from generator to brw_fs_lower_regioning.cpp. (Suggested by
   Francisco)
 * Apply to verx10 >= 125.. (Suggested by Francisco)

Cc: 23.1 <mesa-stable>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com> (v1)
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22569>
 2023-04-20 11:41:10 -07:00
Lionel Landwerlin 2e2491b76c anv: enable shaderStorageImageReadWithoutFormat on Gfx12.5+ 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22552>
 2023-04-19 06:04:52 +00:00
Michel Dänzer 73e9cf6062 anv/format: Fix GetPhysicalDeviceSparseImageFormatProperties definition 
To match its declaration (and the corresponding definition in Vulkan
headers).

Pointed out by GCC 13:

../src/intel/vulkan/anv_formats.c:1597:6: warning: conflicting types for ‘anv_GetPhysicalDeviceSparseImageFormatProperties’ due to enum/integer mismatch; have ‘void(struct VkPhysicalDevice_T *, VkFormat,  VkImageType,  uint32_t,  VkImageUsageFlags,  VkImageTiling,  uint32_t *, VkSparseImageFormatProperties *)’ {aka ‘void(struct VkPhysicalDevice_T *, VkFormat,  VkImageType,  unsigned int,  unsigned int,  VkImageTiling,  unsigned int *, VkSparseImageFormatProperties *)’} [-Wenum-int-mismatch]
 1597 | void anv_GetPhysicalDeviceSparseImageFormatProperties(
      |      ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
In file included from ../src/intel/vulkan/anv_private.h:123,
                 from ../src/intel/vulkan/anv_formats.c:24:
src/intel/vulkan/anv_entrypoints.h:122:30: note: previous declaration of ‘anv_GetPhysicalDeviceSparseImageFormatProperties’ with type ‘void(struct VkPhysicalDevice_T *, VkFormat,  VkImageType,  VkSampleCountFlagBits,  VkImageUsageFlags,  VkImageTiling,  uint32_t *, VkSparseImageFormatProperties *)’ {aka ‘void(struct VkPhysicalDevice_T *, VkFormat,  VkImageType,  VkSampleCountFlagBits,  unsigned int,  VkImageTiling,  unsigned int *, VkSparseImageFormatProperties *)’}
  122 |   VKAPI_ATTR void VKAPI_CALL anv_GetPhysicalDeviceSparseImageFormatProperties(VkPhysicalDevice physicalDevice, VkFormat format, VkImageType type, VkSampleCountFlagBits samples, VkImageUsageFlags usage, VkImageTiling tiling, uint32_t* pPropertyCount, VkSparseImageFormatProperties* pProperties);
      |                              ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22517>
 2023-04-18 09:49:44 +00:00
Lionel Landwerlin 3beaaa9ae8 anv: drop lowered storage images code 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22302>
 2023-04-18 08:38:55 +00:00