anv: enable shaderUniformBufferArrayNonUniformIndexing

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22624>

src/intel/vulkan/anv_device.c

@@ -1296,7 +1296,7 @@ void anv_GetPhysicalDeviceFeatures2(
       .shaderInputAttachmentArrayDynamicIndexing          = false,
       .shaderUniformTexelBufferArrayDynamicIndexing       = true,
       .shaderStorageTexelBufferArrayDynamicIndexing       = true,
-      .shaderUniformBufferArrayNonUniformIndexing         = false,
+      .shaderUniformBufferArrayNonUniformIndexing         = true,
       .shaderSampledImageArrayNonUniformIndexing          = true,
       .shaderStorageBufferArrayNonUniformIndexing         = true,
       .shaderStorageImageArrayNonUniformIndexing          = true,

src/intel/vulkan/anv_nir_apply_pipeline_layout.c

@@ -730,6 +730,13 @@ try_lower_direct_buffer_intrinsic(nir_builder *b,
 
    nir_address_format addr_format = descriptor_address_format(desc, state);
 
+   /* Although we could lower non uniform binding table accesses with
+    * nir_opt_non_uniform_access, we might as well use an A64 message and
+    * avoid the loops inserted by that lowering pass.
+    */
+   if (nir_intrinsic_access(intrin) & ACCESS_NON_UNIFORM)
+      return false;
+
    if (nir_deref_mode_is(deref, nir_var_mem_ssbo)) {
       /* 64-bit atomics only support A64 messages so we can't lower them to
        * the index+offset model.
@@ -738,12 +745,6 @@ try_lower_direct_buffer_intrinsic(nir_builder *b,
           !state->pdevice->info.has_lsc)
          return false;
 
-      /* Normal binding table-based messages can't handle non-uniform access
-       * so we have to fall back to A64.
-       */
-      if (nir_intrinsic_access(intrin) & ACCESS_NON_UNIFORM)
-         return false;
-
       if (!descriptor_has_bti(desc, state))
          return false;