16ffa0a490
r300: fix locked_zbuffer leak
...
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36447 >
2025-12-09 14:49:46 +00:00
31aea50093
r300: fix overflow in r300_draw_elements_immediate
...
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36447 >
2025-12-09 14:49:46 +00:00
bf453aa004
r300: fix dummy_vs leak
...
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36447 >
2025-12-09 14:49:46 +00:00
f8363b8d25
driconf: use vk_dont_care_as_load workaround for Spilled!
...
Unity's Vulkan backend used by Spilled! requires the vk_dont_care_as_load
workaround to achieve correct rendering. Observed on Turnip, in GMEM mode.
Signed-off-by: Zan Dobersek <zdobersek@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38863 >
2025-12-09 07:48:32 +01:00
2fbc722dcf
anv: Fix misplaced assertion in anv_scratch_pool_alloc
...
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com >
Fixes: ee42a489https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38861 >
2025-12-09 06:13:53 +00:00
68bb5d9e49
kk: enable shaderClipDistance
...
Since Metal doesn't pass clip distance into the fragment shader, we have to
do it ourselves. The CLIP_DIST0/1 varying slots are used to represent the
user-defined varyings we use to pass them from vertex to fragment and
a new intrinsic is added to represent the write to the built-in
clip_distance variable. Since the CLIP_DIST0/1 varying slots are not affected
by opt_varyings, there can be potential interface mismatches so the machinery
in msl_iomap.c is refactored to allow them to be output as a series of scalars
rather than vectors.
Reviewed-by: Aitor Camacho <aitor@lunarg.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38839 >
2025-12-08 23:09:53 -05:00
6d6634e805
kk: Expose 4444 and ycbcr 2plane 444 formats
...
Extensions:
- VK_EXT_4444_formats
- VK_EXT_ycbcr_2plane_444_formats
Features:
- formatA4R4G4B4
- formatA4B4G4R4
- ycbcr2plane444Formats
Signed-off-by: Aitor Camacho <aitor@lunarg.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38831 >
2025-12-09 01:19:32 +00:00
4a58046caa
kk: Fix emulated format's swizzle
...
Signed-off-by: Aitor Camacho <aitor@lunarg.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38831 >
2025-12-09 01:19:31 +00:00
dd4a1a50f5
kk: Expose ASTC HDR formats
...
Extensions:
- VK_EXT_texture_compression_astc_hdr
Features:
- textureCompressionASTC_HDR
Signed-off-by: Aitor Camacho <aitor@lunarg.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38831 >
2025-12-09 01:19:31 +00:00
2112eb4aa4
kk: Match float formats to actual Metal features (union of Apple and Mac2)
...
Signed-off-by: Aitor Camacho <aitor@lunarg.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38851 >
2025-12-09 01:02:52 +00:00
d5b05d53e4
kk: Expose shaderImageGatherExtended
...
Limit gather offsets to hardware's limit [-8, 7].
Reviewed-By: Arcady Goldmints-Orlov <arcady@lunarg.com >
Signed-off-by: Aitor Camacho <aitor@lunarg.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38846 >
2025-12-08 23:49:01 +00:00
9649eee307
meson: Use /Zc:enumTypes enables C++ conforming enum underlying type and enumerator type deduction
...
The detail is at https://learn.microsoft.com/en-us/cpp/build/reference/zc-enumtypes?view=msvc-170
For example:
enum Enum {
A = 'A',
B = sizeof(A)
};
static_assert(B == 1); // previously failed, now succeeds under /Zc:enumTypes
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38639 >
2025-12-08 22:47:13 +00:00
6e3598177b
freedreno/common: Add A840 and X2-85
...
Add support for A840 and X2-85. Despite slice count, differences in
memory bus and clks, they are architecturally similar from the PoV of
the UMD.
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450 >
2025-12-08 22:12:12 +00:00
11364f4ee2
freedreno: gen8 support
...
Enable gen8 support. Sysmem, gmem, and binning work. DEQP gles2/3/31
tests are passing.
LRZ is not supported yet, and will follow later.
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450 >
2025-12-08 22:12:12 +00:00
469a19f66b
freedreno/computerator: gen8 support
...
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450 >
2025-12-08 22:12:12 +00:00
46dd4b166e
freedreno/a6xx: Fix VSC_BIN_SIZE for gen8
...
It was missed that this register changed for larger bin sizes. Use a
common bitset for all related gen8 regs, and change the field names for
earlier gens to match so the generated register packers dtrt.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450 >
2025-12-08 22:12:12 +00:00
237e93aa45
freedreno/a6xx: Add gen8 query support
...
The RBBM_PIPESTAT_x regs moved around. Re-work how we figure out the
appropriate reg offset to take this into account by using the templated
reg packers.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450 >
2025-12-08 22:12:12 +00:00
e15ac3b043
freedreno/a6xx: Drop log_pipeline_stats()
...
This was useful when we didn't have docs and had to figure out which
counter was which. That is no longer an issue.
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450 >
2025-12-08 22:12:12 +00:00
a818287fd6
freedreno/registers: gen8 support
...
Co-developed-by: Akhil P Oommen <akhilpo@oss.qualcomm.com >
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450 >
2025-12-08 22:12:11 +00:00
6c39336f2f
freedreno/registers: More gen8 prep
...
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450 >
2025-12-08 22:12:11 +00:00
01041c858e
freedreno/a6xx: Handle tess_bo size differences for gen8
...
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450 >
2025-12-08 22:12:10 +00:00
222c005c01
freedreno/fdl: Fix gen8 buffer depth
...
Seems we need to program it to 1, otherwise all ssbo writes (and reads?)
end up in index 0.
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450 >
2025-12-08 22:12:10 +00:00
5310672706
freedreno/fdl: Fix gen8 TEX_LINE_OFFSET
...
It is in units of bits.
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450 >
2025-12-08 22:12:10 +00:00
4f6076f531
freedreno/registers: Add TPL1_MODE_CNTL bitfields
...
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450 >
2025-12-08 22:12:09 +00:00
be6c181ae6
freedreno/registers: Fix gen8 UBWC array pitch
...
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450 >
2025-12-08 22:12:08 +00:00
5c98f110da
ir3: Add new cat3 instructions
...
b13 encodes alternate opcode meanings for new instructions with
otherwise the same encoding (ie. src precision implied by opc).
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450 >
2025-12-08 22:12:08 +00:00
aadd1dabde
ir3: dp2acc is removed in gen8
...
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450 >
2025-12-08 22:12:08 +00:00
9d3102048e
ir3: Add new cat2 instructions
...
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450 >
2025-12-08 22:12:07 +00:00
937625c391
ir3: Fix gen8 ldc encoding
...
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450 >
2025-12-08 22:12:06 +00:00
e53c605adf
ir3: Add mova.r encoding
...
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450 >
2025-12-08 22:12:06 +00:00
688d62381c
ir3: Use ldc.u in preamble
...
r63.u isn't a shared reg, so we weren't setting the .u bit on ldc. But
in a preamble, we should be.
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450 >
2025-12-08 22:12:05 +00:00
d146a31ee1
ir3: Add mova .u bit
...
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450 >
2025-12-08 22:12:05 +00:00
4bc01d11b0
ir3: Add cat3 flut src encoding
...
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450 >
2025-12-08 22:12:05 +00:00
c35b5f9726
ir3: Add cat3 alt immed encoding
...
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450 >
2025-12-08 22:12:04 +00:00
1c7c4b4807
ir3: Add cat1 (sat) bit
...
Appears to be present at least as far back as gen7.
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450 >
2025-12-08 22:12:04 +00:00
69e0536203
ir3: Add (eostsc)
...
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450 >
2025-12-08 22:12:03 +00:00
fa5be473b8
ir3: Add disasm test macro for gen8
...
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450 >
2025-12-08 22:12:03 +00:00
189e494249
ir3: Add (sy) before end of preamble when necessary
...
We need to ensure GPR writes completes before the end of the preamble
to avoid writes landing after another preamble has already started.
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450 >
2025-12-08 22:12:02 +00:00
a48e4b8340
ir3: Extract out helper for nop flags
...
Extract out a helper to add a flag to a nop, potentially re-using a
previous nop where possible.
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450 >
2025-12-08 22:12:01 +00:00
d1df3b4e39
ir3: Limit CS lock/unlock quirk
...
We don't need this universally for everything >= gen7.
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450 >
2025-12-08 22:12:01 +00:00
e00bff2513
ir3: Fix cat3 latency
...
The rule about only needing two cycles for 3rd src of cat3 instructions
only applies to variants of mad.
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450 >
2025-12-08 22:12:01 +00:00
02a4cc622d
ir3: Fix gen8 instruction timings
...
non_alu is still 6. But AFAICT none of this changes since a7xx so these
were probably wrong on a7xx as well.
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450 >
2025-12-08 22:12:01 +00:00
3e7f200e1f
ir3: Skip non-bindless ldc warmups
...
Non bindless UBOs are pushed in cmdstream, so warmup instructions should
be unnecessary. And cause hangs on gen8.
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450 >
2025-12-08 22:12:01 +00:00
d3e479b5c5
freedreno/registers: Fix gen8 swizzle enum
...
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450 >
2025-12-08 22:12:00 +00:00
39bf9c0222
freedreno/registers: pm4 updates for gen8
...
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450 >
2025-12-08 22:12:00 +00:00
fa45a48843
freedreno: Add gen8 chip template-fu
...
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450 >
2025-12-08 22:12:00 +00:00
d786b6ad3e
freedreno/drm-shim: Add a830
...
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450 >
2025-12-08 22:11:59 +00:00
49c2271f26
freedreno/common: Add placeholder a8xx device
...
Enough to have a gpu-id so that cffdump, disasm tests, etc, function.
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450 >
2025-12-08 22:11:59 +00:00
aa112be635
freedreno/common: Make max tile dimensions a param
...
This value may differ between SKUs within a given generation. So make
them parameters.
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450 >
2025-12-08 22:11:59 +00:00
96d6755e1f
freedreno: Add gen8 device info
...
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450 >
2025-12-08 22:11:58 +00:00
Pavel Ondračka