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freedreno/registers: Fix gen8 UBWC array pitch

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Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
This commit is contained in:
Rob Clark
2025-10-21 11:59:49 -07:00
committed by Marge Bot
parent 5c98f110da
commit be6c181ae6
2 changed files with 2 additions and 2 deletions
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src/freedreno/fdl/fd6_view.cc
+1 -1
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@@ -389,7 +389,7 @@ fdl6_view_init(struct fdl6_view *view, const struct fdl_layout **layouts,
A8XX_TEX_MEMOBJ_4_FLAG_LO(ubwc_addr);
descriptor[5] |= A8XX_TEX_MEMOBJ_5_FLAG_HI(ubwc_addr >> 32) |
A8XX_TEX_MEMOBJ_5_FLAG_BUFFER_PITCH(ubwc_pitch);
descriptor[8] |= A8XX_TEX_MEMOBJ_8_FLAG_ARRAY_PITCH(layout->ubwc_layer_size >> 2) |
descriptor[8] |= A8XX_TEX_MEMOBJ_8_FLAG_ARRAY_PITCH(layout->ubwc_layer_size) |
A8XX_TEX_MEMOBJ_8_FLAG_BUFFER_LOGW(util_logbase2_ceil(DIV_ROUND_UP(width, block_width))) |
A8XX_TEX_MEMOBJ_8_FLAG_BUFFER_LOGH(util_logbase2_ceil(DIV_ROUND_UP(height, block_height)));
}
src/freedreno/registers/adreno/a8xx_descriptors.xml
+1 -1
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@@ -97,7 +97,7 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
<bitfield name="UV_OFFSET_V" low="26" high="27" type="ufixed" radix="2"/> <!-- CHROMA_MIDPOINT_Y -->
</reg32>
<reg32 offset="8" name="8">
<bitfield name="FLAG_ARRAY_PITCH" low="0" high="14" shr="4" type="uint"/> <!-- FLAG_BUFFER_ARRAY_PITCH -->
<bitfield name="FLAG_ARRAY_PITCH" low="0" high="14" shr="12" type="uint"/> <!-- FLAG_BUFFER_ARRAY_PITCH -->
<!-- log2 size of the first level, required for mipmapping -->
<bitfield name="FLAG_BUFFER_LOGW" low="24" high="27" type="uint"/>
<bitfield name="FLAG_BUFFER_LOGH" low="28" high="31" type="uint"/>