AlexIndustrial/mesa
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
177,320 Commits 1 Branch 0 Tags
10e75aae1bddee9795b1ff04ffd656b0da79b5b5
Commit Graph

10133 Commits

Author SHA1 Message Date
Lionel Landwerlin 10e75aae1b intel/nir: rerun lower_tex if it lowers something 
nir_lower_tex can lower tg4 coords into tg4 offset which on DG2+ we
also need to lower into constant offsets.

Unfortunately the nir_lower_tex pass is not able to lower the
instructions it itself generates, so the easy fix for when
nir_lower_tex lowers tg4 coords into tg4 offsets is to rerun the pass.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9735
Cc: mesa-stable
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Tested-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25015>
 2023-09-05 13:35:51 +00:00
Lionel Landwerlin 40d7cb4000 intel/measure: track batch buffer sizes 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24628>
 2023-09-05 11:50:02 +00:00
Lionel Landwerlin 2108742257 anv: reuse cmd_buffer::total_batch_size 
This was left unused after 624ac55721 ("anv: move total_batch_size to
anv_batch"). We're now going to use it to store the total amount of
commands written in a command buffer.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24628>
 2023-09-05 11:50:02 +00:00
Lionel Landwerlin 94e3e05b93 anv: rename total_batch_size 
This name is confusing, the real thing it represents is the allocated
amount of batch space.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24628>
 2023-09-05 11:50:02 +00:00
Chris Spencer b492f73f87 anv/android: Enable shared presentable image support 
Signed-off-by: Chris Spencer <spencercw@gmail.com>
Reviewed-by: Roman Stratiienko <r.stratiienko@gmail.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24941>
 2023-09-05 10:02:24 +00:00
Tapani Pälli 672155ee04 anv: implement Wa_14018912822 
When MSAA is enabled, instead of using BLENDFACTOR_ZERO use CONST_COLOR,
CONST_ALPHA and supply zero by using blend constants.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24714>
 2023-09-04 18:57:33 +00:00
Lionel Landwerlin 8a32614a18 isl/tilememcpy_test: add multiple tile testing 
Also verify that there is no out-of-bounds accesses.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Aditya Swarup <aditya.swarup@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13391>
 2023-09-02 21:49:05 -07:00
Aditya Swarup a6c8ddb596 intel/isl: Linear to Tile-4 conversion unittest 
Add unittest to test conversion of data from linear to
Tile-4 format based on bit swizzling conversion info
mentioned in Bspec.

Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13391>
 2023-09-02 21:49:05 -07:00
Aditya Swarup 4f0d02902e intel/isl: Convert Tile4 texture to linear format 
Add memcpy function to convert Tile-4 4KB texture to linear
format.

Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13391>
 2023-09-02 21:49:05 -07:00
Aditya Swarup a648ee7a70 intel/isl: Convert linear texture to Tile4 format 
Add memcpy function to convert linear data to Tile 4 format.
Tile 4 format consists of 4KB block divided into chunks of 512B.
Each 512B chunk/block is comprised of 8 64B blocks arranged in
Y-tile format.

Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13391>
 2023-09-02 21:49:05 -07:00
Aditya Swarup d16eac17d8 intel/isl: Unittest for linear to Ytile conversion 
Add unittests for linear to tiled and tiled to linear texture
conversions for Ytile. The test prints the source/output buffer
in hex format with debug flags to verify the result.

Linear to tile conversion fills the linear buffer with values
based on the OWORD index number i.e., OWORD3 will contain
all values filled as 0x03 and
OWORD3 = 0x03030303030303030303030303030303.

The Y-tile to Linear tile conversion uses a similar logic to place
the tiled values in a manner that will result in a linear buffer with
OWORDs filled according to index number as mentioned above.

Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13391>
 2023-09-02 21:49:03 -07:00
Rohan Garg ca7ae1a53f blorp: drop undefined macro 
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 97d6ceaf04 ("intel: Remove GEN_IS_HASWELL macro")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25011>
 2023-09-03 03:04:26 +00:00
Rohan Garg 86e8ba4d32 anv: use the lineage number for WA 
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: d0669f3ede ("intel/dev: switch defect identifiers to use lineage numbers")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25011>
 2023-09-03 03:04:26 +00:00
Rohan Garg cbc4916661 anv: drop dead ifdef 
The GFX_VERX10 macro doesn't exist and we no longer use
SCRATCH_SURFACE_STATE_POOL_SIZE.

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: b3f6e5dc70 ('anv: remove incorrect ifdef')
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25011>
 2023-09-03 03:04:26 +00:00
Alyssa Rosenzweig fd114ab706 ci: Disable WHL jobs 
Timing out all day.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2023-09-02 15:43:01 -04:00
Lionel Landwerlin 4066f05fe4 anv: enable standard Y tiles 
We kept those tilings disabled up to know. Now that ISL has proper
support for them, remove this.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
 2023-09-01 23:22:18 +00:00
Jason Ekstrand db4488a2dc anv: Align memory VA to support for Ys, Tile64 tiled images 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
 2023-09-01 23:22:18 +00:00
Aditya Swarup e03f3b646c isl: enable Tile64 for 3D images 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
 2023-09-01 23:22:18 +00:00
Jason Ekstrand e956f6ad30 intel/isl: Allow Ys tiling 
Ys & Yf are both implemented in ISL now, we still have some Yf issues
to investigate. Instead of disabling them in ISL, we disable them in
the two drivers.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
 2023-09-01 23:22:18 +00:00
Lionel Landwerlin 4ac46dbb46 isl: reorder tiling selection 
Select tilings in this order :
  - recommended Y tilings
  - Yf tilings
  - Ys/Tile64 tilings
  - legacy tilings (W, X) & Linear

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
 2023-09-01 23:22:18 +00:00
Lionel Landwerlin af559c48d3 intel/aux_map: correctly program tiling mode for Ys 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
 2023-09-01 23:22:18 +00:00
Lionel Landwerlin 3c6d003d9f blorp: allow 3D blits/copies on Ys/Yf/Tile64 tiling 
The data in Ys/Yf/Tile64 tiled images is arranged differently for 2D &
3D images. Therefore we cannot assume that we will use 2D images for
blits/copies.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
 2023-09-01 23:22:18 +00:00
Lionel Landwerlin e182f5770d isl: disable CCS on Ys/Yf 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
 2023-09-01 23:22:18 +00:00
Lionel Landwerlin 4e36aa507e isl: disable miptails on gfx12 with yuv formats 
A number of CTS tests are failing, like :

   dEQP-VK.ycbcr.format.b8g8r8g8_422_unorm.vertex_optimal

Failures are reproduced on simulation.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
 2023-09-01 23:22:18 +00:00
Lionel Landwerlin aa31683dde isl: disallow miptails on planar formats 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
 2023-09-01 23:22:18 +00:00
Lionel Landwerlin 7ee41c162d isl: add Gfx12/12.5 restriction on 3D surfaces & compression 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
 2023-09-01 23:22:18 +00:00
Jason Ekstrand 63c86a95b2 intel/isl: Disallow CCS on 3D surfaces with miptails 
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
 2023-09-01 23:22:18 +00:00
Jason Ekstrand 46f45d62d1 intel/isl: Start using miptails 
This commit adds the code for choosing where to start the miptail and
enables miptails by default unless the client driver passes
info->min_miptail_start_level >= info->levels.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
 2023-09-01 23:22:18 +00:00
Jason Ekstrand a42d808b71 intel/isl: Support miptails in isl_surf_get_uncompressed_surf 
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
 2023-09-01 23:22:18 +00:00
Lionel Landwerlin 866af3d8fa isl: make isl_surf_get_uncompressed_surf robust to argument accesses 
Since the input & output arguments can point to the same location in
memory, if you ever access the input after writing the output you're
in trouble.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
 2023-09-01 23:22:18 +00:00
Jason Ekstrand 988fa2006a intel/isl: Add support for computing offsets with miptails 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
 2023-09-01 23:22:17 +00:00
Lionel Landwerlin 1ada5f5490 intel/isl: Add a max_miptail_levels field to isl_tile_info 
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
 2023-09-01 23:22:17 +00:00
Jason Ekstrand b1862a0964 intel/isl: Add initial data-structure support for miptails 
This commit just adds a miptail start field to isl_surf and wires it up
in the RENDER_SURFACE_STATE and 3DSTATE_DEPTH code.  We also add a
minimum miptail LOD so that client drivers have a knob to control the
miptails a bit.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
 2023-09-01 23:22:17 +00:00
Jason Ekstrand 68ac5c2165 intel/isl: Support Yf/Ys tiling in emit_depth_stencil_hiz 
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
 2023-09-01 23:22:17 +00:00
Jason Ekstrand 01b50c9dac intel/isl: Support Yf/Ys tiling in surf_fill_state 
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
 2023-09-01 23:22:17 +00:00
Jason Ekstrand 6f90d6d228 intel/isl: Support Ys, Yf & Tile64 in isl_surf_get_uncompressed_surf 
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
 2023-09-01 23:22:17 +00:00
Jason Ekstrand 4ef7b074e7 intel/isl: Indent uncompressed surface code 
We're about to add separate code for Yf/Ys and this helps keep the diff
reasonable.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
 2023-09-01 23:22:17 +00:00
Jason Ekstrand 9a4e9848ad intel/isl: Fill out the correct phys_total_extent for Ys/Yf/Tile64 
With these tilings, everything is aligned to a tile and the tiled
surface size calculations will handle the array stride for us.  We need
to provide an accurate 4D size so that 3D and multisampled images get
tiled correctly.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
 2023-09-01 23:22:17 +00:00
Jason Ekstrand 9421998e95 intel/isl: Use the depth field of phys_level0_sa for GFX4_2D 3D surfaces 
This makes things a tiny bit stickier in isl_calc_phys_total_extent_el
but will be worth it when we enable Yf and Ys.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
 2023-09-01 23:22:17 +00:00
Lionel Landwerlin 390d53e13f isl: disallow TileYs/Yf on 3D storage images on Gfx9/11 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
 2023-09-01 23:22:17 +00:00
Lionel Landwerlin 15648dcbba isl: add a usage flag to request 2D/3D compatible views 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
 2023-09-01 23:22:17 +00:00
Lionel Landwerlin 7c5015e181 isl: disable Yf/Ys/Tile64 tilings for 1D images 
The ICL+ PRMs show that this is not a supported thing anymore for
Ys/Yf and there isn't really much use for it in Vulkan/Sparse.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
 2023-09-01 23:22:17 +00:00
Lionel Landwerlin 6cde6b1d1a intel/isl: Disallow Yf, Ys and Tile64 for 3D depth/stencil surfaces 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
 2023-09-01 23:22:17 +00:00
Jason Ekstrand 911832e9cf intel/isl: Implement correct tile size calculations for Ys/Yf 
The tile size calculations use a clever bit of math to make them short
and simple.  We add unit tests to assert that they identically match the
tables in the PRM.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
 2023-09-01 23:22:17 +00:00
Jason Ekstrand e230ef329b intel/isl: Add ICL variants of Yf and Ys tiling 
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
 2023-09-01 23:22:17 +00:00
Jason Ekstrand fa625aea3d intel/isl: Rename ISL_TILING_Yf/s to ISL_TILING_SKL_Yf/s 
The Yf and Ys tilings change a bit between SKL and later generations so
we have to be able to distinguish between them.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
 2023-09-01 23:22:17 +00:00
Lionel Landwerlin 298e8dee61 isl: program 3DSTATE_HIER_DEPTH_BUFFER_BODY::TiledMode as documented 
Since this value is 0, it doesn't change anything, but it's just good
practice like we did for Gfx12.5 right above.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
 2023-09-01 23:22:17 +00:00
Lionel Landwerlin 3e9f366b70 genxml/gfx12: rename Tiled Resource Mode 
To match documentation.

BSpec 46965

TGL PRMs, Volume 2d: Command Reference: Structures, 3DSTATE_HIER_DEPTH_BUFFER_BODY

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
 2023-09-01 23:22:17 +00:00
Lionel Landwerlin cc985bb2ad genxml/gfx11: remove Tiled Resource Mode field from HIER_DEPTH_BUFFER 
This field doesn't exist according to documentation. Only a MBZ.

BSpec 6511

ICL PRMs, Volume 2a - Command Reference: Instructions (Command
Opcodes) 3DSTATE_HIER_DEPTH_BUFFER

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
 2023-09-01 23:22:16 +00:00
Lionel Landwerlin 34d5db0583 anv: add missing ISL storage usage 
ISL makes a bunch of decision on programming (MOCS,
RENDER_SURFACE_STATE values) based on this flag. It's important to set
it if we're going to use an image as storage.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
 2023-09-01 23:22:16 +00:00