AlexIndustrial/mesa
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
193,007 Commits 1 Branch 0 Tags
0e27df45213e51d8e2e68f43dcbb5d5b32958d33
Commit Graph

193007 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Marek Olšák 0e27df4521 radeonsi/gfx12: fix VS output corruption with streamout 
We increased VS_EXPORT_COUNT to 8 for streamout in gfx10_shader_ngg,
but we forgot to increase the attribute ring stride, causing all waves
except the first one to get corrupted VS outputs.

Fixes: f703dfd1bb - radeonsi: add gfx12

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30503>
 2024-08-05 19:35:39 +00:00
Marek Olšák 8b3e02587e radeonsi: program OREO_MODE optimally on gfx11.x and gfx12 
This fixes a rare performance regression since we stopped setting OREO_MODE.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30503>
 2024-08-05 19:35:39 +00:00
Marek Olšák dd7e33d5b9 radeonsi/gfx11: prepare for CWSR 
CWSR = compute wave save restore

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30503>
 2024-08-05 19:35:39 +00:00
Marek Olšák 07a0b5e2f2 radeonsi/gfx12: fix register programming to fix GPU hangs 
Fixes: f703dfd1bb - radeonsi: add gfx12

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30503>
 2024-08-05 19:35:39 +00:00
Marek Olšák 83b88c54ba radeonsi: fix buffer coherency issues on gfx6-8,12 due to missing PFP->ME sync 
This fixes random GPU hangs on gfx12 due to incoherent indirect buffer data,
causing random indirect vertex and instance counts, which timeouts if
the random numbers are large.

Fixes: a8abbbb172 - radeonsi: remove r600_pipe_common.h

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30503>
 2024-08-05 19:35:39 +00:00
Marek Olšák 72e6cefe00 radeonsi: don't set TC_L2_dirty in si_query_hw_get_result_resource 
It's set automatically by si_launch_grid_internal_ssbos.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30503>
 2024-08-05 19:35:39 +00:00
Marek Olšák ebc5116e70 radeonsi: ensure TC_L2_dirty is set if we don't sync after internal SSBO blits 
There was a case where if we don't sync, we wouldn't set TC_L2_dirty either,
which could cause problems later.

Fixes: f703dfd1bb - radeonsi: add gfx12

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30503>
 2024-08-05 19:35:39 +00:00
Marek Olšák e4b3848fde radeonsi/gfx12: fix a GPU hang due to an invalid packet with window rectangles 
I guess incorrect packet interrupts have been enabled, so this started hanging.

radeon_set_context_reg_seq shouldn't be used with gfx12_set_context_reg.

Fixes: f703dfd1bb - radeonsi: add gfx12

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30503>
 2024-08-05 19:35:39 +00:00
Marek Olšák de83b5ef77 ac/surface/gfx12: fix setting tile_swizzle 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30503>
 2024-08-05 19:35:39 +00:00
Thomas H.P. Andersen 0f665b8178 nvk: EXT_post_depth_coverage 
EXT_post_depth_coverage was already wired up but the tests were
failing. Through experimentation I found that running them in
combination with SET_HYBRID_ANTI_ALIAS_CONTROL would cause the
tests to fail.

This patch simply skips SET_HYBRID_ANTI_ALIAS_CONTROL when post
depth coverage is in use

Test results for *post_depth_cover*:

Test run totals:
  Passed:        21/104 (20.2%)
  Failed:        0/104 (0.0%)
  Not supported: 83/104 (79.8%)
  Warnings:      0/104 (0.0%)
  Waived:        0/104 (0.0%)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29194>
 2024-08-05 19:26:04 +00:00
Faith Ekstrand 4090aa064f nvk: Set POST_PS_INITIAL_COVERAGE 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29194>
 2024-08-05 19:26:04 +00:00
Faith Ekstrand 1ba4bc2ada nvk: Don't force sample shading when gl_SampleMaskIn[] is read 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29194>
 2024-08-05 19:26:04 +00:00
Faith Ekstrand b8d50542c0 nak,nir: Rework gl_SampleMaskIn[] handling 
The pixld.covmask instruction returns the coverage mask for the entire
pixel being shaded, not the set of samples covered by the current FS
invocation as required by GL/Vulkan.  In order to get the GL/Vulkan
behavior, we have to mask off samples not covered by the current FS
invocation.

Previously, we handled this by masking by 1 << gl_SampleID.  This
required us to force full sample shading whenever gl_SampleMaskIn[] was
used.  Otherwise, we didn't know what to mask.  Instead, this commit
switches us to using an array in CB0 which has a sample mask for each
sample, representing the set of samples in that sample's pass.  Masking
by this allows us to get the full range of variability provided by
NVIDIA's multi-pass MSAA hardware.  It also allows us to eliminate the
workaround that forced per-sample shading for gl_SampleMaskIn[] because
we can adjust the masks from the API side as needed.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29194>
 2024-08-05 19:26:04 +00:00
Faith Ekstrand 761874ea85 nak: Sample locations are byte-aligned 
Fixes: cc33cafcac ("nak/nir: Use an indirect load for sample locations")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29194>
 2024-08-05 19:26:03 +00:00
Faith Ekstrand 315b788c7b nvk: Move nvk_sample_location to NAK 
It's part of the NAK compiler interface so that's where it should live.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29194>
 2024-08-05 19:26:03 +00:00
Paulo Zanoni 644dcc0337 anv: disable CCS for Source2 games on Xe2 
Dota 2 and Counter-Strike 2 really want to be able to allocate memory
for both VkImages and VkBuffers from the same memory type. Xe2's
special compression-only memory type does not support buffers, which
makes these games crash. Disable CCS on these games as a workaround.

This is a temporary workaround as we're still working towards a
long-term solution (either by fixing the engine or finding a way
better expose our memory types).

Backport-to: 24.2
Fixes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11520
Fixes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11521
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30481>
 2024-08-05 18:36:46 +00:00
Paulo Zanoni b4f5a04223 anv: don't expose the compressed memory types when DEBUG_NO_CCS 
These memory types are useless when CCS is disabled, don't leave them
there so they don't confuse applications.

Backport-to: 24.2
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30481>
 2024-08-05 18:36:46 +00:00
Caio Oliveira ba3fd5dc57 intel/brw: Don't retype load_subgroup_invocation result to signed 
The values are small unsigned integers, so their signed representation
will be the same -- the sign conversion is not needed.  As a result the
extra MOV can be elided by the optimizations.

Fossil-db results for DG2

```
Totals:
Instrs: 151779000 -> 151761591 (-0.01%)
Cycle count: 12743968649 -> 12742826024 (-0.01%); split: -0.01%, +0.00%
Max live registers: 31834993 -> 31834996 (+0.00%)

Totals from 17018 (2.70% of 631450) affected shaders:
Instrs: 2381740 -> 2364331 (-0.73%)
Cycle count: 76798588 -> 75655963 (-1.49%); split: -1.70%, +0.22%
Max live registers: 378921 -> 378924 (+0.00%)
```

and TGL

```
Totals:
Instrs: 149812033 -> 149794080 (-0.01%); split: -0.01%, +0.00%
Cycle count: 11534727002 -> 11534929834 (+0.00%); split: -0.01%, +0.01%
Spill count: 42510 -> 42511 (+0.00%); split: -0.00%, +0.01%
Fill count: 75100 -> 75101 (+0.00%); split: -0.00%, +0.00%
Max live registers: 31727318 -> 31727321 (+0.00%)

Totals from 17421 (2.76% of 630458) affected shaders:
Instrs: 3092614 -> 3074661 (-0.58%); split: -0.58%, +0.00%
Cycle count: 286061417 -> 286264249 (+0.07%); split: -0.32%, +0.39%
Spill count: 11538 -> 11539 (+0.01%); split: -0.02%, +0.03%
Fill count: 21359 -> 21360 (+0.00%); split: -0.01%, +0.01%
Max live registers: 418954 -> 418957 (+0.00%)
```

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30508>
 2024-08-05 18:05:45 +00:00
Felix DeGrood 86c4e89aa2 anv: fix src_hash dumping for compute shaders 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30495>
 2024-08-05 16:46:42 +00:00
Alejandro Piñeiro 28df772935 v3dv: expose Vulkan 1.3 
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10896

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29476>
 2024-08-05 15:10:24 +00:00
Alejandro Piñeiro 3ae4da4ea7 v3dv: update conformanceVersion to 1.3.8.3 
As we used as reference to check if we fully pass Vulkan 1.3

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29476>
 2024-08-05 15:10:24 +00:00
Alejandro Piñeiro 781622ba5b v3dv/device: set value for maxInlineUniformTotalSize 
Fixes the following test, as far as you enable Vulkan 1.3 (if not it
is skipped):

dEQP-VK.api.info.vulkan1p3_limits_validation.max_inline_uniform_total_size

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29476>
 2024-08-05 15:10:24 +00:00
José Roberto de Souza 132c5cdeb9 intel/dev: Support new topology type with SIMD16 EUs 
Xe KMD will now report the different topology mask types based on the
type of the EU of running platform.
With this we don't need to divide the EU count by 2 in intel_perf.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30127>
 2024-08-05 07:01:47 -07:00
José Roberto de Souza 3da911b092 intel: Sync xe_drm.h 
Sync xe_drm.h with f2881dfdaaa9 ("drm/xe/oa/uapi: Make bit masks unsigned").

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30127>
 2024-08-05 07:00:10 -07:00
Job Noorman 3a26925cc7 ir3/postched: don't prioritize instructions with soft delays 
Before resorting to scheduling instructions based on max_delay only,
postsched would prioritize instructions that have no hard delay (i.e.,
delays for which nops should be inserted) but might still have soft
delays (for which ss/sy needs to be inserted). Removing this has a
slight negative effect on nops but improves sstall/systall. This seems
to improve actual render pass time.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30437>
 2024-08-05 12:20:03 +00:00
Job Noorman c7de402ad5 ir3/postsched: include ss/sy delay in max_delay 
max_delay is a measure for the maximum delay from a node to the end of a
block so it should include all types of delay.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30437>
 2024-08-05 12:20:03 +00:00
Job Noorman 8f52f941ef ir3/postsched: remove unused delay field 
Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30437>
 2024-08-05 12:20:03 +00:00
Job Noorman 8cc269a16f ir3/postsched: fix calculation of max_delay 
max_delay is a measure for the maximum delay from a node to the end of a
block. However, the current calculation would include the delay of the
node itself (which is the maximum delay from the node's sources). At the
point a node is scheduled, this source delay might already be much
smaller (or even zero) because its sources have hopefully been scheduled
much earlier. This means the max_delay value would be an overestimate of
the actual delay from the node to the block's end.

This commit fixes this and makes sure max_delay is always the maximum
delay from a node to the end of the block from the point where the node
is scheduled.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30437>
 2024-08-05 12:20:03 +00:00
Job Noorman db21255d72 ir3/postsched: improve debug state dumping 
- Print all different delay info per node.
- Allow the DAG to be dumped up to a customizable depth.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30437>
 2024-08-05 12:20:03 +00:00
Collabora's Gfx CI Team 1d35b2f343 Uprev Piglit to 4a62c26721a47552a96416a134b789a813dd51a6 
https://gitlab.freedesktop.org/mesa/piglit/-/compare/582f5490a124c27c26d3a452fee03a8c85fa9a5c...4a62c26721a47552a96416a134b789a813dd51a6

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30254>
 2024-08-05 10:45:38 +00:00
Rhys Perry 8f3d0fbad7 aco: don't transform v_interp_p2_f32 with constant into fma 
Since v_interp_p2_f32 with constant operands only happens on GFX11.5, this
should actually be fine in all cases where this is currently possible
(GFX11.5+ allows DPP with scalar src1). However, it does fail validation
because we haven't updated that yet.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Fixes: bee487df48 ("aco/gfx11.5+: use vinterp for fddx/fddy")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30477>
 2024-08-05 09:32:24 +00:00
Rhys Perry 911fdce0b6 aco: fix validation of v_s_ opcodes 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Fixes: 284b9965e8 ("aco/gfx11.5+: allow sgpr dst for trans ops and use pseudo scalar ops on gfx12")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30477>
 2024-08-05 09:32:24 +00:00
Karol Herbst b3e925a21b rusticl/kernel: properly respect device thread limits per dimension 
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30504>
 2024-08-04 23:00:08 +00:00
Karol Herbst b2225b9437 zink: lower 8/16 bit alu ops vk spirv doesn't allow 
Cc: mesa-stable
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30504>
 2024-08-04 23:00:08 +00:00
Karol Herbst 39ec184db6 zink: lower 64 bit find_lsb, ufind_msb and bit_count 
Cc: mesa-stable
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30504>
 2024-08-04 23:00:08 +00:00
Eric Engestrom 9155e0a887 ci/deqp-runner: fix --fraction-start in non-parallel jobs 
`CI_NODE_INDEX` is only defined in `parallel:` jobs.

Without this, we end up with `--fraction-start --fraction 1`, which is
obviously invalid but somehow it hasn't blown up (yet).

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30462>
 2024-08-04 20:40:26 +00:00
David Heidelberg 366e7e2ddc freedreno: drop dEQP hacks 
Not necessary since ceece45b2b ("freedreno: drop hack for old dEQP").

Reviewed-by: Rob Clark <robclark@freedesktop.org>
Signed-off-by: David Heidelberg <david@ixit.cz>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30497>
 2024-08-04 05:27:30 +09:00
Lionel Landwerlin 97f6a296e3 anv: better signal new frames to utrace 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29944>
 2024-08-03 16:03:15 +03:00
Lionel Landwerlin bc523e8949 util/debug: update parse_enable_string to deal with +all/-all 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29944>
 2024-08-03 16:03:13 +03:00
Lionel Landwerlin 4b1e3b8515 u_trace: add csv output 
Some of my colleagues have scripts using CSV format for measuring
frame timing.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29944>
 2024-08-03 16:03:07 +03:00
Lionel Landwerlin 78ae7ab856 anv/hasvk: add indirect tracepoint arguments 
Gives visibility on some indirect parameter dispatches :
  - draw count
  - compute dispatch size

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29944>
 2024-08-03 16:03:04 +03:00
Lionel Landwerlin 0a17035b5c u_trace: add support for indirect data 
Allows a driver to declare indirect arguments for its tracepoints and
pass an address. u_trace will request a copy of the data which should
be implemented on the command processor.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Co-Authored-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Reviewed-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29944>
 2024-08-03 16:03:00 +03:00
Lionel Landwerlin cb27b9541b u_trace: remove timestamp reference in allocations 
We want to reduce the buffer allocations for other type of data than
timestamps.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29944>
 2024-08-03 16:02:56 +03:00
Lionel Landwerlin 4347ccbe57 u_trace: rework tracepoint argument declaration 
We're about to add indirect arguments, having a better way to describe
arguments (as capture/storage) will be useful.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29944>
 2024-08-03 16:02:53 +03:00
Lionel Landwerlin 29bf1547c0 u_trace: add mako exception printouts 
Useful for debug

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29944>
 2024-08-03 16:02:19 +03:00
Echo J e14d1f5bc0 util: Fix the integer addition in os_time_get_absolute_timeout() 
This should fix glClientWaitSync() timing out too early with a INT64_MAX
timeout on radeonsi

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11615
Fixes: 7316cc92f3 ("gallium/os: add conversion and wait functions for absolute timeouts")
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30476>
 2024-08-03 04:19:28 +00:00
David Heidelberg dafc4476f7 freedreno: Implement fast clear_buffer for Adreno 6xx and 7xx 
Increase performance of
 - OpenGL ARB_clear_buffer_object impl.
 - OpenCL clEnqueueFillBuffer implementation

Reviewed-by: Rob Clark <robclark@freedesktop.org>
Signed-off-by: David Heidelberg <david@ixit.cz>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30284>
 2024-08-03 12:44:32 +09:00
David Heidelberg ddfb8ebf8c freedreno: introduce color format parameter to emit_blit_buffer_dst 
Useful for followup clear_buffer implementation.

Reviewed-by: Rob Clark <robclark@freedesktop.org>
Signed-off-by: David Heidelberg <david@ixit.cz>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30284>
 2024-08-03 12:32:10 +09:00
David Heidelberg 635a40cc5c freedreno: Introduce emit_blit_fini 
De-duplicate the code a bit and prepare for using this in clear_buffer function.

Reviewed-by: Rob Clark <robclark@freedesktop.org>
Signed-off-by: David Heidelberg <david@ixit.cz>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30284>
 2024-08-03 12:32:10 +09:00
Echo J b2f919eaaf d3d10umd: Use pipe_resource_usage enum in translate_resource_usage() 
This should fix a build error with MSVC

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11461
Fixes: 40785d9a52 ("gallium: properly type pipe_resource.usage with the enum")
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Max Ramanouski <max8rr8@gmail.com>
Reviewed-by: Jose Fonseca <jose.fonseca@broadcom.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30172>
 2024-08-02 22:57:19 +00:00