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Author SHA1 Message Date
Sagar Ghuge 46d203c0ab anv: Add secondary companion RCS cmd buffer to primary 
Add secondary buffer's companion RCS command buffer to primary buffer's
companion RCS command buffer for execution if secondary RCS is valid.

v2: (Lionel)
- Fix the primary companion RCS check
- Set batch error

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23661>
 2023-09-07 06:39:06 +00:00
Sagar Ghuge 4d79c2d280 anv: Execute an empty batch to sync main and companion RCS batch 
We need to synchronize main (CCS/BCS) and companion rcs batch, so let's
create an empty batch and make both the batches (CCS/BCS) and companion
RCS batch wait on empty sync batch and signal the fence.

Reason to execute the empty batch is we need to make sure the companion
RCS batch finish as soon as the CCS/BCS batch finish. Preemption could
prevent the companion RCS batch execution and we might end up destroying
the CCS/BCS batch before companion RCS finishes.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23661>
 2023-09-07 06:39:06 +00:00
Sagar Ghuge 0c49d3cf97 anv: Setup companion RCS command buffer submission 
Add all the wait fences from the main (CCS/BCS) command buffer to the
companion RCS command buffer so that the companion RCS batch starts at
the same time as the main (CCS/BCS) batch.

v2:
- Drop unncessary flush (Jose)

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23661>
 2023-09-07 06:39:06 +00:00
Sagar Ghuge a63277ec36 anv: Execute RCS init batch on companion RCS context/engine 
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23661>
 2023-09-07 06:39:06 +00:00
Sagar Ghuge 103512ef3b anv: Move compute specfic bits under compute queue init 
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23661>
 2023-09-07 06:39:06 +00:00
Sagar Ghuge b375302576 anv: Create companion RCS engine 
We need to create companion RCS engine when there is CCS/BCS engine
creation requested.

v2:
- Factor out anv_xe_create_engine code in create_engine (Jose)

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23661>
 2023-09-07 06:39:06 +00:00
Lionel Landwerlin a5f2c8c845 anv: create individual logical engines on i915 when possible 
This enables us to create more logical engines than HW engines are
available. This also brings the uAPI usage closer to what is happening
on Xe.

Rework: (Sagar)
- Correct exec_flag at the time of submission
- Handle device status check
- Set queue parameters

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23661>
 2023-09-07 06:39:06 +00:00
Sagar Ghuge a5e4be45c0 intel: Pass virtual memory address space ID while creating context 
In future patches, we will be creating a separate companion RCS engine
and each engine is created with it's own address space, and we really
don't want. CCS and RCS engine writes should be visible to each other in
order to get the wait/signal mechanism working.

v2:
- Move drm_i915_gem_context_create_ext_setparam out of if block (Lionel)

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23661>
 2023-09-07 06:39:06 +00:00
Sagar Ghuge b73960fc40 intel: Add helper to create/destroy i915 VM 
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23661>
 2023-09-07 06:39:06 +00:00
Sagar Ghuge 13b3d7f741 anv: Handle companion RCS in end/destory/reset code path 
If we have valid companion RCS command buffer, we should
end/destroy/reset in the same fashion as of main command buffer.

v2:
- Add lock around anv_cmd_buffer_destroy (Sagar)

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23661>
 2023-09-07 06:39:06 +00:00
Sagar Ghuge 801523f03d anv: Split out End/Destroy/Reset cmd buffer code into helper 
Since we are going to have companion RCS command buffer, we need to
end/destroy/reset companion RCS command buffer similar to main (CCS/BCS)
command buffer.

It's better to split out common code into helper function so that we can
use it later in this series.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23661>
 2023-09-07 06:39:05 +00:00
Sagar Ghuge edcde0679c anv: Add helper to create companion RCS command buffer 
This helper takes the main command buffer as input and then create a
companion RCS command buffer.

v2:
- Rename anv_get_render_queue_index helper to
  anv_get_first_render_queue_index (Jose)
- Rename RCS command buffer to companion RCS command buffer (Lionel)
- Add early return in anv_get_first_render_queue_index (Lionel)
- Add lock around the function (Jose)
- Move companion rcs command pool creation in device create (Sagar)
- Reset companion RCS cmd buffer (Sagar)

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23661>
 2023-09-07 06:39:05 +00:00
Lionel Landwerlin ceb1c6033b anv: split BLEND_STATE packing from BLEND_STATE_POINTERS emit 
This way when blorp changes the 3DSTATE_BLEND_STATE_POINTERS, we can
just reemit the prior Vulkan state without repacking any of the values
in the BLEND_STATE structure.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24536>
 2023-09-06 20:07:02 +00:00
Lionel Landwerlin 2b5f9cc30a anv: remove unused state emission 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24536>
 2023-09-06 20:07:02 +00:00
Lionel Landwerlin 50f6903bd9 anv: add new low level emission & dirty state tracking 
A single Vulkan state can map to multiple fields in different GPU
instructions. This change introduces the bottom half of a simplified
emission mechanism where we do the following :
          Vulkan runtime state
                   |
                   V
        Intermediate driver state
                   |
                   V
         Instruction programming

This way we can detect that the intermediate state didn't change and
avoid HW instruction emission.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24536>
 2023-09-06 20:07:02 +00:00
Lionel Landwerlin 44656f98d5 anv: split pipeline programming into instructions 
The goal of this change it to move away from a single batch buffer
containing all kind of pipeline instructions to a list of instructions
we can emit separately.

We will later implement pipeline diffing and finer state tracking that
will allow fewer instructions to be emitted.

This changes the following things :

   * instead of having a batch & partially packed instructions, move
     everything into the batch

   * add a set of pointer in the batch that allows us to point to each
     instruction (almost... we group some like URB instructions,
     etc...).

At pipeline emission time, we just go through all of those pointers
and emit the instruction into the batch. No additional packing is
involved.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24536>
 2023-09-06 20:07:02 +00:00
Lionel Landwerlin 758540d741 anv: add a flag tracking occlusion query count change 
We'll use this later to know when to reemit
3DSTATE_STREAMOUT::ForceRendering

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24536>
 2023-09-06 20:07:02 +00:00
Lionel Landwerlin 0ce772bd19 anv: split 3DSTATE_VFG emission 
Leave the static part in genX_pipeline.c and only repack the dynamic
part in genX_gfx_state.c

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24536>
 2023-09-06 20:07:02 +00:00
Lionel Landwerlin 1e081bd680 anv: split 3DSTATE_TE packing between static & dynamic parts 
We can reduce the amount of packing we do by only packing the dynamic
part.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24536>
 2023-09-06 20:07:02 +00:00
Lionel Landwerlin 19c3f3ede4 anv: categorize partial/final pipeline instruction 
The old gfx8 field doesn't apply anymore.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24536>
 2023-09-06 20:07:02 +00:00
Lionel Landwerlin b1614c4e22 anv: rename files to represent their usage 
gfx8_cmd_buffer.c does not apply to gfx8 anymore for instance, it can
also be included in all builds.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24536>
 2023-09-06 20:07:01 +00:00
Lionel Landwerlin a1f7e7d93e anv: move all dynamic state emission to cmd_buffer_flush_dynamic_state 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24536>
 2023-09-06 20:07:01 +00:00
Lionel Landwerlin 047c0ba44b intel/decoder: implement accumulated prints 
Useful when you want to compare 2 batches with different ordering in
instruction emission. Also when the driver tries to avoid re-emitting
state.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24536>
 2023-09-06 20:07:01 +00:00
Lionel Landwerlin 2c3a51573a intel/anv: batch stats util 
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24536>
 2023-09-06 20:07:01 +00:00
Lionel Landwerlin 1fdc089e9c anv: change anv_batch_emit_merge to also do packing 
Instead of having that function do only merging of 2 sets of dwords,
it can also do the packing of the new dynamic values. This saves us a
bunch of local structures to declare and calling the packing functions
ourselves.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24536>
 2023-09-06 20:07:01 +00:00
Lionel Landwerlin 5c287385c2 anv: remove ReorderMode from pipeline 3DSTATE_GS emission 
This bit is set in the dynamic state emission. This is currently not
breaking anything because LEADING=0.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 71ebd9b9d7 ("anv,hasvk: respect provoking vertex setting on geometry shaders")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24536>
 2023-09-06 20:07:01 +00:00
Lionel Landwerlin adfa4f0453 blorp: remove unused variable 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24719>
 2023-09-06 19:34:28 +00:00
Lionel Landwerlin 9231f24be1 hasvk: add state cache invalidation back before fast clears 
Prior to 87149cc545, blorp added a state cache invalidation prior to
fast clears. This got dropped on Hasvk.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 87149cc545 ("blorp: update and move fast clear PIPE_CONTROLs to drivers")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24719>
 2023-09-06 19:34:28 +00:00
Lionel Landwerlin c9739e8912 intel/fs: limit register flag interaction of FIND_*LIVE_CHANNEL 
Those instructions do not access the flag registers on Gfx8+. Removing
the interaction enables CSE to remove more of those instructions.

Results are a bit mixed (DG2 vulkan fossils):

  ACO:
  Totals from 127 (5.97% of 2128) affected shaders:
  Instrs: 139966 -> 138972 (-0.71%); split: -0.85%, +0.14%
  Cycles: 1685747 -> 1667480 (-1.08%); split: -2.35%, +1.26%
  Max live registers: 10582 -> 10544 (-0.36%)
  Max dispatch width: 1048 -> 1040 (-0.76%)

  Cyberpunk 2077:
  Totals from 2879 (27.95% of 10301) affected shaders:
  Instrs: 4264789 -> 4225666 (-0.92%); split: -1.01%, +0.09%
  Cycles: 72380209 -> 71619521 (-1.05%); split: -1.63%, +0.58%
  Subgroup size: 30624 -> 30632 (+0.03%)
  Spill count: 98 -> 101 (+3.06%)
  Fill count: 90 -> 93 (+3.33%)
  Scratch Memory Size: 8192 -> 9216 (+12.50%)
  Max live registers: 217807 -> 217098 (-0.33%); split: -0.59%, +0.26%
  Max dispatch width: 23792 -> 24112 (+1.34%)

  Gaining 40 SIMD16 shaders

  Rise Of The Tomb Raider:
  Totals from 622 (5.06% of 12289) affected shaders:
  Instrs: 437380 -> 434760 (-0.60%); split: -0.72%, +0.12%
  Cycles: 261843085 -> 261580703 (-0.10%); split: -0.73%, +0.63%
  Max live registers: 27731 -> 27766 (+0.13%); split: -1.01%, +1.14%
  Max dispatch width: 5832 -> 5432 (-6.86%); split: +0.27%, -7.13%

  Loosing 26 SIMD32 shaders

  Strange Brigade:
  Totals from 1298 (31.48% of 4123) affected shaders:
  Instrs: 1504408 -> 1487968 (-1.09%); split: -1.17%, +0.08%
  Cycles: 20735976 -> 20443216 (-1.41%); split: -1.60%, +0.19%
  Max live registers: 89911 -> 89957 (+0.05%)

DG2 shader-db run:

  total instructions in shared programs: 23130895 -> 23130036 (<.01%)
  instructions in affected programs: 260956 -> 260097 (-0.33%)
  helped: 234
  HURT: 101
  helped stats (abs) min: 1 max: 54 x̄: 6.36 x̃: 4
  helped stats (rel) min: 0.05% max: 8.16% x̄: 2.01% x̃: 1.90%
  HURT stats (abs)   min: 1 max: 37 x̄: 6.23 x̃: 3
  HURT stats (rel)   min: 0.02% max: 5.67% x̄: 0.89% x̃: 0.55%
  95% mean confidence interval for instructions value: -3.62 -1.51
  95% mean confidence interval for instructions %-change: -1.33% -0.94%
  Instructions are helped.

  total loops in shared programs: 6071 -> 6071 (0.00%)
  loops in affected programs: 0 -> 0
  helped: 0
  HURT: 0

  total cycles in shared programs: 898610645 -> 898557166 (<.01%)
  cycles in affected programs: 18308201 -> 18254722 (-0.29%)
  helped: 315
  HURT: 48
  helped stats (abs) min: 1 max: 19312 x̄: 404.23 x̃: 128
  helped stats (rel) min: 0.02% max: 28.98% x̄: 3.92% x̃: 2.65%
  HURT stats (abs)   min: 2 max: 14478 x̄: 1538.60 x̃: 409
  HURT stats (rel)   min: <.01% max: 23.24% x̄: 3.34% x̃: 0.41%
  95% mean confidence interval for cycles value: -333.68 39.03
  95% mean confidence interval for cycles %-change: -3.51% -2.41%
  Inconclusive result (value mean confidence interval includes 0).

  total spills in shared programs: 5964 -> 5964 (0.00%)
  spills in affected programs: 0 -> 0
  helped: 0
  HURT: 0

  total fills in shared programs: 6909 -> 6909 (0.00%)
  fills in affected programs: 0 -> 0
  helped: 0
  HURT: 0

  total sends in shared programs: 1040266 -> 1040266 (0.00%)
  sends in affected programs: 0 -> 0
  helped: 0
  HURT: 0

  LOST:   3
  GAINED: 1

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24553>
 2023-09-06 14:47:40 +00:00
Jordan Justen 8c8fca53fd intel/genxml: Fix comparing xml when node counts differ 
This fix is more relevant to MR !20593. Normally when sorting the
number of nodes will be equivalent today, so this bug will not be
encountered. But in !20593, we can shrink (--import) or grow the
number of elements (--flatten) when the genxml_import.py tool is used.

Fixes: e60a0b1616 ("intel/genxml: Move sorting & writing into GenXml class")
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24902>
 2023-09-06 07:18:47 +00:00
Jordan Justen d8038c8d09 intel/genxml: Ignore tail leading/trailing whitespace in node_validator() 
When importing or flattening genxml with the genxml_import.py script
in MR !20593, it can lead to the tail portion of xml items differing
in whitespace.

If we strip the trailing and leading whitespace from the tail string,
and the strings are equivalent, then we can consider the xml items to
be equivalent.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24903>
 2023-09-06 06:51:48 +00:00
Jordan Justen 5d37359f32 intel/dev/xe: Move placeholder subslice info into XEHP_FEATURES 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24418>
 2023-09-05 23:02:42 -07:00
Chris Spencer c29e3d5205 anv/video: use correct enum value for max level IDC 
Signed-off-by: Chris Spencer <spencercw@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24649>
 2023-09-06 05:10:33 +00:00
Jordan Justen 2b128c570b intel/clflush: Add support for clflushopt instruction 
Rework:
 * Split clflushopt into a separate file as recommended by Ken.
   If we enable -mclflush on all driver source compilation, then
   gcc may insert uses of it on processors that don't support it.
 * Add uintptr_t casting to cpu_caps->cacheline usage

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22379>
 2023-09-06 01:39:53 +00:00
Jordan Justen e111d3241a anvil,hasvk: Use intel_flush_range_no_fence to flush command buffers 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22379>
 2023-09-06 01:39:53 +00:00
Jordan Justen 9f20be64e6 intel/common: Add intel_flush_range_no_fence 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22379>
 2023-09-06 01:39:53 +00:00
Jordan Justen 486e7bdbd8 anvil,hasvk: Replace intel_clflush_range with intel_flush_range 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22379>
 2023-09-06 01:39:53 +00:00
Jordan Justen 543a707b7b intel/common: Move intel_clflush.h to intel_mem.h/intel_mem.c 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22379>
 2023-09-06 01:39:53 +00:00
Jordan Justen 735026e811 anvil,hasvk: Rename need_clflush to need_flush 
$ git grep -l need_clflush | xargs sed -i 's/need_clflush/need_flush/g'

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22379>
 2023-09-06 01:39:53 +00:00
antonino aa657247ce vulkan/wsi: add vk_wsi_force_swapchain_to_current_extent driconf 
Add a driconf to force the swapchain size to match
`VkSurfaceCapabilities2KHR::currentExtent` as a workaround for
misbehaved games

Fixes: 6139493ae3 ("vulkan/wsi: return VK_SUBOPTIMAL_KHR for sw/x11 on window resize")
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24818>
 2023-09-06 00:10:41 +00:00
Lionel Landwerlin 10e75aae1b intel/nir: rerun lower_tex if it lowers something 
nir_lower_tex can lower tg4 coords into tg4 offset which on DG2+ we
also need to lower into constant offsets.

Unfortunately the nir_lower_tex pass is not able to lower the
instructions it itself generates, so the easy fix for when
nir_lower_tex lowers tg4 coords into tg4 offsets is to rerun the pass.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9735
Cc: mesa-stable
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Tested-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25015>
 2023-09-05 13:35:51 +00:00
Lionel Landwerlin 40d7cb4000 intel/measure: track batch buffer sizes 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24628>
 2023-09-05 11:50:02 +00:00
Lionel Landwerlin 2108742257 anv: reuse cmd_buffer::total_batch_size 
This was left unused after 624ac55721 ("anv: move total_batch_size to
anv_batch"). We're now going to use it to store the total amount of
commands written in a command buffer.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24628>
 2023-09-05 11:50:02 +00:00
Lionel Landwerlin 94e3e05b93 anv: rename total_batch_size 
This name is confusing, the real thing it represents is the allocated
amount of batch space.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24628>
 2023-09-05 11:50:02 +00:00
Chris Spencer b492f73f87 anv/android: Enable shared presentable image support 
Signed-off-by: Chris Spencer <spencercw@gmail.com>
Reviewed-by: Roman Stratiienko <r.stratiienko@gmail.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24941>
 2023-09-05 10:02:24 +00:00
Tapani Pälli 672155ee04 anv: implement Wa_14018912822 
When MSAA is enabled, instead of using BLENDFACTOR_ZERO use CONST_COLOR,
CONST_ALPHA and supply zero by using blend constants.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24714>
 2023-09-04 18:57:33 +00:00
Lionel Landwerlin 8a32614a18 isl/tilememcpy_test: add multiple tile testing 
Also verify that there is no out-of-bounds accesses.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Aditya Swarup <aditya.swarup@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13391>
 2023-09-02 21:49:05 -07:00
Aditya Swarup a6c8ddb596 intel/isl: Linear to Tile-4 conversion unittest 
Add unittest to test conversion of data from linear to
Tile-4 format based on bit swizzling conversion info
mentioned in Bspec.

Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13391>
 2023-09-02 21:49:05 -07:00
Aditya Swarup 4f0d02902e intel/isl: Convert Tile4 texture to linear format 
Add memcpy function to convert Tile-4 4KB texture to linear
format.

Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13391>
 2023-09-02 21:49:05 -07:00
Aditya Swarup a648ee7a70 intel/isl: Convert linear texture to Tile4 format 
Add memcpy function to convert linear data to Tile 4 format.
Tile 4 format consists of 4KB block divided into chunks of 512B.
Each 512B chunk/block is comprised of 8 64B blocks arranged in
Y-tile format.

Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13391>
 2023-09-02 21:49:05 -07:00