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10573 Commits

Author SHA1 Message Date
Samuel Pitoiset 50b5a9a4a0 anv: use common entrypoints for VK_KHR_create_renderpass2 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9601>
 2021-03-24 11:21:53 +00:00
Mauro Rossi cb4287608a android: anv: add libcutils shared dependency 
My previous patch merged as 2b1930a50a was incomplete

Fixes the following building error:

FAILED: out/target/product/x86_64/obj/SHARED_LIBRARIES/vulkan.anv_intermediates/LINKED/vulkan.anv.so
...
ld.lld: error: undefined symbol: property_get
>>> referenced by os_misc.c:193 (external/mesa/src/util/os_misc.c:193)
>>>               os_misc.o:(os_get_option) in archive out/target/product/x86_64/obj/STATIC_LIBRARIES/libmesa_util_intermediates/libmesa_util.a

Cc: 21.0 <mesa-stable@lists.freedesktop.org>
Fixes: eeecc21d93 ("util: Add property_get() fallback for android")
Fixes: 2b1930a50a ("android: radv: add libcutils shared dependency")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9744>
 2021-03-22 22:52:13 +01:00
Marcin Ślusarz b0452f150e intel/aub_viewer: fix decoding of sampler states 
There's only 1 sampler state behind
3DSTATE_SAMPLER_STATE_POINTERS[_VS|_HS|_DS|_GS|_PS] and
3DSTATE_SAMPLER_STATE_POINTERS.[PointertoVSSamplerState|PointertoPSSamplerState|PointertoGSSamplerState].

Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9707>
 2021-03-22 08:36:55 +00:00
Marcin Ślusarz 186301a232 intel/aub_viewer: drop bogus check 
state_addr == bo.addr, bo.size==0 is handled by another check

Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9707>
 2021-03-22 08:36:55 +00:00
Marcin Ślusarz 2b5f9602b7 intel/aub_viewer: catch invalid sampler state pointer 
Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9707>
 2021-03-22 08:36:55 +00:00
Marcin Ślusarz 08f8677b29 intel/batch_decoder: assert on invalid sampler pointer 
Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9707>
 2021-03-22 08:36:55 +00:00
Marcin Ślusarz 56cd91bc7c intel/batch_decoder: fix decoding of sampler states 
There's only 1 sampler state behind
3DSTATE_SAMPLER_STATE_POINTERS[_VS|_HS|_DS|_GS|_PS] and
3DSTATE_SAMPLER_STATE_POINTERS.[PointertoVSSamplerState|PointertoPSSamplerState|PointertoGSSamplerState].

Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9707>
 2021-03-22 08:36:55 +00:00
Marcin Ślusarz cd0f9cdb6e intel/batch_decoder: drop bogus check 
state_addr == bo.addr, bo.size==0 is handled by another check

Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9707>
 2021-03-22 08:36:55 +00:00
Marcin Ślusarz bb8ee5f52d intel/batch_decoder: catch invalid sampler state pointer 
Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9707>
 2021-03-22 08:36:55 +00:00
Jason Ekstrand 731ea06758 intel/tools: Handle BINDING_TABLE_POOL_ALLOC in batch decoding 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9729>
 2021-03-20 12:46:50 -05:00
Jason Ekstrand 79d9c914ae intel/genxml: Make BindingTablePoolEnable a bool 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9729>
 2021-03-20 12:46:50 -05:00
Jason Ekstrand 05e133a84a intel/tools: Handle GT_MODE in the batch decoder 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9729>
 2021-03-20 12:46:50 -05:00
Jason Ekstrand b2421f7b44 intel/tools: Handle milti-LRI in the batch decoder 
Context batches tend to have a lot of multi-LRI and, if we want to be
able to parse those registers nicely, we really handle it.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9729>
 2021-03-20 12:33:18 -05:00
Jason Ekstrand 65077cdf57 intel/genxml: Binding table pointers are 15 bits on GFX version 12.5+ 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9729>
 2021-03-20 12:33:16 -05:00
Kenneth Graunke 6fb93465bd intel/genxml: Add a partial GT_MODE definition for Gen11+. 
I chose to drop "HW" from the name of this field because on Gen11
it applies to both HW and SW binding tables, so it's a bit of a
misnomer.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9729>
 2021-03-20 12:32:55 -05:00
Jordan Justen 16d453da7f genxml/gen12: 3D_MODE bits 31:16 are no longer must-be-one 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9505>
 2021-03-19 09:07:37 +00:00
Michel Dänzer 05bf12ccb6 intel/tools: Use subprocess.Popen to read output directly from a pipe 
Instead of using tempfiles to communicate between child & parent
process. The latter sometimes resulted in hitting the meson timeout if
there was high filesystem pressure.

Fixes: ccaa5b034f "intel/tools: rewrite run-test.sh in python"
Reviewed-by: Dylan Baker <dylan.c.baker@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9528>
 2021-03-19 08:50:37 +00:00
Lionel Landwerlin 9d947127d3 anv: use the device size of CS prefetch to pad secondary buffer calls 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9679>
 2021-03-18 20:08:45 +00:00
Lionel Landwerlin 33bc2977e5 intel/mi_builder: use device info to use the right CS prefetch size 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9679>
 2021-03-18 20:08:45 +00:00
Lionel Landwerlin beb680aae4 intel/dev: store size of CS prefetch 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9679>
 2021-03-18 20:08:45 +00:00
Jordan Justen df5607d2ef anv: Use fallback paths if DRM_I915_QUERY_ENGINE_INFO fails 
Anvil can handle if this call fails, but not if we assert. :)

Reported-by: Brian Paul <brianp@vmware.com>
Fixes: 5d84c764fd ("anv: Gather engine info from i915 if available")
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9664>
 2021-03-18 00:54:29 +00:00
Jason Ekstrand 91192696e6 intel/fs: Add support for 16-bit A64 float and integer atomics 
The messages for those 16-bit operations still use 32-bit sources and
destinations, so expand them accordingly when building the payload.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8750>
 2021-03-18 00:13:40 +00:00
Lionel Landwerlin 8b6d22109f intel/fs/vec4: add missing dependency in write-on-write fixed GRFs 
If we load constant data using pull constant SENDS, and we later load
that register with some other data, we can end up in a situation where
we don't track the initial fixed register write and therefore end up
using uninitialized registers.

This tracks write-on-write of fixed GRFs like we do for normal virtual
GRFs.

v2: Fix post_alloc_reg case (Jason)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9667>
 2021-03-17 23:25:02 +00:00
Jason Ekstrand 4079279051 anv/apply_pipeline_layout: Add support for A64 descriptor access 
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8635>
 2021-03-17 17:49:59 +00:00
Jason Ekstrand b704d03efd anv: Do UBO loads with global addresses for bindless 
This makes UBO loads in the variable pointers or bindless case work just
like SSBO loads in the sense that they use A64 messages and 64-bit
global addresses.  The primary difference is that we have an
optimization in anv_nir_lower_ubo_loads which uses a (possibly
predicated) block load message when the offset is constant so we get
roughly the same performance as we would from plumbing load_ubo all the
way to the back-end.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8635>
 2021-03-17 17:49:59 +00:00
Jason Ekstrand 61749b5a15 anv: Add a pass for lowering A64 UBO access 
Instead of load_global_constant_offset/bounded, we want to use the
Intel-specific block load intrinsic whenever we can.  This way we get
the same wide block loads that we usually use for constant offset UBO
pulls with a binding table.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8635>
 2021-03-17 17:49:59 +00:00
Jason Ekstrand bd65e4d199 anv/apply_pipeline_layout: Use the new helpers for images 
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8635>
 2021-03-17 17:49:59 +00:00
Jason Ekstrand 4113a3750c anv/apply_pipeline_layout: Use the new helpers for early lowering 
This also means that some of the newly added helpers need to grow a bit
to support VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_DATA_EXT.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8635>
 2021-03-17 17:49:59 +00:00
Jason Ekstrand 93126b641c anv/apply_pipeline_layout: Rework the desc_addr_format helper 
We're about to add a new helper which is more detailed.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8635>
 2021-03-17 17:49:59 +00:00
Jason Ekstrand f95134a0fe anv/apply_pipeline_layout: Refactor all our descriptor address builders 
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8635>
 2021-03-17 17:49:59 +00:00
Jason Ekstrand 42de744155 anv/apply_pipeline_layout: Apply dynamic offsets in load_ssbo_descriptor 
This function has exactly two call sites.  The first is where we had
these calculations before.  The second only cares about the size of the
SSBO so all the extra code we emit will be dead.  However, NIR should
easily clean that up and this lets us consolidate things a bit better.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8635>
 2021-03-17 17:49:59 +00:00
Jason Ekstrand 8a61e3a0c0 anv: Zero out the last dword of UBO/SSBO descriptors in the shader 
This way, NIR can constant fold it.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8635>
 2021-03-17 17:49:59 +00:00
Jason Ekstrand 422798caef anv: Rework the 64bit_bounded_global resource index format 
Instead of packing the descriptor offset into the packed portion, use
that unused channel we have lying around.  This potentially allows for
larger descriptor sets.  We also re-arrange the components a bit to make
it more like the 64bit_bounded_global memory address format.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8635>
 2021-03-17 17:49:59 +00:00
Jason Ekstrand e06144a818 anv: Use 64bit_global_32bit_offset for SSBOs 
This has the advantage of giving us cheaper address calculations because
we can calculate in 32 bits first and then do a single 64x32 add.  It
also lets us delete a bunch of code for dealing with descriptor
dereferences (vulkan_resource_reindex, and friends) because our bindless
SSBO pointers are now vec4s regardless of whether or not we're doing
bounds checking.  This also unifies UBOs and SSBOs.  The one down-side
is that, in certain variable pointers cases, it may end up burning more
memory and/or increasing register pressure.  This seems like a worth-
while trade-off.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8635>
 2021-03-17 17:49:59 +00:00
Jason Ekstrand e13246e053 anv/apply_pipeline_layout: Add some switch statements 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8635>
 2021-03-17 17:49:59 +00:00
Jason Ekstrand f872a26991 anv/apply_pipeline_layout: Plumb through a UBO address format 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8635>
 2021-03-17 17:49:59 +00:00
Jason Ekstrand 2b8f76b128 anv/apply_pipeline_layout: Move bounds checking later for index/offset 
Instead of doing the array check at the load_vulkan_resource_index
intrinsic, stuff it in the vec2 and handle it at load_vulkan_descriptor
time.  This allows the bounds check to take any re-index intrinsics into
account.  This only affects variablePointers + SSBOs + Gen7.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8635>
 2021-03-17 17:49:59 +00:00
Jason Ekstrand 2beba9dd5a anv/apply_pipeline_layout: Run DCE between the early and late passes 
This allows us to ignore UBOs in the late code going forward.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8635>
 2021-03-17 17:49:59 +00:00
Jason Ekstrand a7fe687bde anv/apply_pipeline_layout: Lower UBO loads in the early pass 
We're about to enable bindless UBOs via A64 memory access like we do for
SSBOs.  In order to prevent 100% of UBOs from hitting that path, we
enable them in the early lowering.  This way we'll still get binding
table-based UBO access for any non-bindless ones.  In particular, we
need this for UBO pushing to work.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8635>
 2021-03-17 17:49:59 +00:00
Jason Ekstrand 799a931d12 anv/apply_pipeline_layout: Rework the early pass index/offset helpers 
Rewrite them all to work on an index/offset vec2 instead of some only
returning the index.  This means SSBO size handling is a tiny bit more
complicated but it will also mean we can use them for descriptor buffers
properly.

This also fixes a bug where we weren't bounds-checking re-index
intrinsics because we applied the bounds check at the tail of the
recursion and not at the beginning.

Fixes: 3cf78ec2bd "anv: Lower some SSBO operations in..."
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8635>
 2021-03-17 17:49:58 +00:00
Jason Ekstrand cdb88f67dc anv/apply_pipeline_layout: Refactor descriptor chasing code 
This makes things a bit more generic for use in the next commit.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8635>
 2021-03-17 17:49:58 +00:00
Jason Ekstrand 0aa3d68206 anv: Use nir_shader_instructions_pass in apply_pipeline_layout 
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8635>
 2021-03-17 17:49:58 +00:00
Jason Ekstrand bfe92b83db anv: Use load_global_constant for shader constants 
NIR can do a bit better job optimizing this version.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8635>
 2021-03-17 17:49:58 +00:00
Jason Ekstrand 1ce3660a5a intel/fs,rt: Add a predicate to load_global_const_block 
This allows us to do bounds checked A64 block load without the it being
counted as control-flow by NIR.  This means that NIR optimizations like
CSE will be able to work on these the same as a regular load.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8635>
 2021-03-17 17:49:58 +00:00
Iago Toral Quiroga 1e4abf1fe3 vulkan/util: call glsl_type_singleton_init_or_ref from vk_instance_init 
v2: link libvulkan_util with libglsl so it can find the glsl singleton symbols.
v3: link with libcompiler instead of libglsl (Jason)

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Dylan Baker <dylan.c.baker@intel.com>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com> for the v3dv bits.
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com> for the turnip bits.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> for the radv bits.
Acked-by: Dave Airlie <airlied@redhat.com> for the lvp bits.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9457>
 2021-03-17 08:15:36 +01:00
Timur Kristóf d70e017c17 anv: Use ASSERTED for results that are only used in asserts. 
This gets rid of unused variable warnings for these results.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9634>
 2021-03-17 03:47:23 +00:00
Timur Kristóf d7a94cae18 anv: Use unreachable() in anv_genX. 
This gets rid of unused variable warnings on genX_thing, because
now the compiler will think that the unknown hardware generation
case is unreachable.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9634>
 2021-03-17 03:47:23 +00:00
Timur Kristóf 17bc587f88 intel/compiler: Make room for maximum dest size in nir_emit_texture. 
The maximum dest_size is 5, not 4.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9634>
 2021-03-17 03:47:23 +00:00
Timur Kristóf eb378e4cd0 intel/compiler: Use assume() instead of assert() for array bounds. 
This should make both GCC and clang happy and make them believe that
the array bounds are not exceeded.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9634>
 2021-03-17 03:47:23 +00:00
Anuj Phogat b505db3864 intel: Simplify few version checks involving G4X 
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9608>
 2021-03-16 16:40:12 +00:00