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Author SHA1 Message Date
Chad Versace 96f4568b63 anv/image: In vkCreateDmaBufImageINTEL use modifiers 
In vkCreateDmaBufImageINTEL, use VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT.

No intended change in publicly visible behavior.

I really don't want to update this soon-to-be-removed function, but this
change is necessary to avoid upcoming assertion failures. In particular,
we will soon assert that the image has a modifier if and only if it has
modifier tiling.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1466>
 2021-04-08 14:15:54 +00:00
Chad Versace 12e8e20802 anv/image: Fix tiling if VkImageSwapchainCreateInfoKHR 
We incorrectly used VK_IMAGE_TILING_OPTIMAL when the original swapchain
image had VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT. When we soon begin
using a different memory layout for modifier images, this mismatch would
have produced undefined behavior.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1466>
 2021-04-08 14:15:54 +00:00
Chad Versace de870cc4b2 anv/image: Simplify assertions in anv_image_from_swapchain() 
No intended change in behavior.

Conceptual diff:
  |- assert(swapchain_image->apples == (pCreateInfo->apples + MORE));
  |  local_create_info->apples = pCreateInfo->apples + MORE;
  |+ assert(swapchain_image->apples == local_create_info->apples);

And, where appropriate:
  |- local_create_info->orange = X;
  |+ /* See spec anchor #swapchain-wsi-image-create-info .  */
  |+ assert(local_create_info->orange == X);

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1466>
 2021-04-08 14:15:54 +00:00
Chad Versace 0845cabc72 vulkan: Track dependencies of Python imports 
The meson.build was unaware of transitive dependencies introduced by
Python imports.

Android still needs fixing. But I did not update the Android files lest
I break the build.

Ideally, we would fix this by using a Python runner that generates
a depfile, similar to how meson creates depfiles for C files by passing
flags -MD -MQ -MF to gcc. But this patch gets the job done, without
stalling on the ideal general solution, by manually tracking the Python
imports in new 'foo_depend_files' variables.

CC: mesa-stable@lists.freedesktop.org
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1466>
 2021-04-08 14:15:54 +00:00
Lionel Landwerlin 49be175a4b intel/fs: limit OW reads to 8 owords on XeHP+ 
We can only use 16 OW reads/writes on SLM.

v2: Update comment (Curro)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
BSpec: 47652
Fixes: 369eab9420 ("intel/fs: Emit code for Gen12-HP indirect compute data")
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10082>
 2021-04-08 09:25:38 +00:00
Lionel Landwerlin 655251ad30 anv: put correct number of BT prefetch for compute on XeHP+ 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10084>
 2021-04-08 09:17:35 +00:00
Mike Blumenkrantz 387189a955 intel: avoid dumping null cs sampler/binding states 
this crashes the driver

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10077>
 2021-04-07 14:24:08 +00:00
Jason Ekstrand 26c3a509de intel: Drop gen_device_info::has_resource_streamer 
We've never done anything with that HW and it was removed in ICL.
There's no point in carrying around the useless field.

Acked-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10069>
 2021-04-07 13:33:18 +00:00
Lionel Landwerlin 33b2daab1a intel/compiler: lower bit sizes in NIR postprocessing 
It appears that between preprocess & postprocess some descriptor
lowering introduces 8bit types in the shader, so run the lower bit
size again to make sure we don't have any unsupported types in our
shader.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: e06144a818 ("anv: Use 64bit_global_32bit_offset for SSBOs")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4478
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9705>
 2021-04-06 23:21:30 +03:00
Alejandro Piñeiro 1e0a69afa7 vulkan: track number of bindings instead of max binding for CreateDescriptorSetLayout 
As that handles better, and more clear, the case of bindingCount being
zero. For the case of Anvil and Turnip, this avoids allocating a
non-needed binding when bindingCount is zero.

Inspired on radv, that was what it was doing so far.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4526

Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Hyunjun Ko <zzoon@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9905>
 2021-04-05 20:17:53 +00:00
Jason Ekstrand cc2a4ff880 anv: Fix coverage masks for VK_EXT_conservative_rasterization 
Earlier, I just tried to copy what iris was doing and, as it turns out,
copied it wrong.  Also, Vulkan doesn't have a concept of getting the
conservative coverage in the shader.  The spec for SampleMask says:

    "Decorating a variable with the SampleMask built-in decoration will
    make any variable contain the coverage mask for the current fragment
    shader invocation."

And the spec for conservative rasterization says

    "When overestimate conservative rasterization is enabled, rather
    than evaluating coverage at individual sample locations, a
    determination is made of whether any portion of the pixel (including
    its edges and corners) is covered by the primitive. If any portion
    of the pixel is covered, then all bits of the coverage mask for the
    fragment corresponding to that pixel are enabled."

Putting these two together and you get what the Intel HW docs say for
ICMS_NORMAL:

    "Input Coverage masks based on inner conservatism and factors in
    SAMPLE_MASKs. If Pixel is conservatively fully covered all samples
    are enabled."

So I'm pretty sure based on this that the right thing to do here is to
ignore conservative rasterization and leave it set to ICMS_NORMAL
whenever we're not in the post-depth-coverage special case.

While we're here, fix the silly indentation.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4565
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: d5b56debde "anv: Implement VK_EXT_conservative_rasterization"
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10017>
 2021-04-04 17:39:32 +00:00
Alyssa Rosenzweig 06ebbde630 vulkan: Deduplicate mesa stage conversion 
Across every driver...

v2: Add casts to appease -fpermissive used on CI.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9477>
 2021-04-03 17:34:39 +00:00
Anuj Phogat 051b7e1925 intel: Rename WA_### to Wa_### 
Commands used to do the changes:
export SEARCH_PATH="src/intel src/gallium/drivers/iris src/mesa/drivers/dri/i965"
grep -E "WA_[[:digit:]]{10}" -rIl $SEARCH_PATH | xargs sed -ie "s/WA_\([[:digit:]]\{10\}\)/Wa_\1/g"

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9936>
 2021-04-02 18:33:07 +00:00
Anuj Phogat f96c3b8b63 intel: Rename GEN:BUG:### to Wa_### 
Commands used to do the changes:
export SEARCH_PATH="src/intel src/gallium/drivers/iris src/mesa/drivers/dri/i965"
grep -E "GEN:BUG:" -rIl $SEARCH_PATH | xargs sed -ie "s/GEN\(:BUG:\)/Wa_/g"

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9936>
 2021-04-02 18:33:07 +00:00
Anuj Phogat 69c3578c8b intel: Rename GEN_{ALL, LT, ..} macros to GFX_{ALL, LT, ..} 
Commands used to do the changes:
export SEARCH_PATH="src/intel src/gallium/drivers/iris src/mesa/drivers/dri/i965"
grep -E "GEN_" -rIl $SEARCH_PATH | xargs sed -ie "s/GEN_\(ALL\|GE\|GT\|LT\|LE\)\([^[:alnum:]]\)/GFX_\1\2/g"

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9936>
 2021-04-02 18:33:07 +00:00
Anuj Phogat ddb04b31fd intel: Remove unused MAKE_GEN macro 
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9936>
 2021-04-02 18:33:07 +00:00
Anuj Phogat e7e55af4d6 intel: Rename GENx keyword to GFXx 
Commands used to do the changes:
export SEARCH_PATH="src/intel src/gallium/drivers/iris src/mesa/drivers/dri/i965"
grep -E "GEN[[:digit:]]+" -rIl $SEARCH_PATH | xargs sed -ie "s/GEN\([[:digit:]]\+\)/GFX\1/g"

Exclude the changes to modifiers:
grep -E "I915_.*GFX" -rIl $SEARCH_PATH | xargs sed -ie "s/\(I915_.*\)GFX/\1GEN/g"

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9936>
 2021-04-02 18:33:07 +00:00
Anuj Phogat 1d296484b4 intel: Rename Genx keyword to Gfxx 
Commands used to do the changes:
export SEARCH_PATH="src/intel src/gallium/drivers/iris src/mesa/drivers/dri/i965"
grep -E "Gen[[:digit:]]+" -rIl $SEARCH_PATH | xargs sed -ie "s/Gen\([[:digit:]]\+\)/Gfx\1/g"

Exclude changes in src/intel/perf/oa-*.xml:
find src/intel/perf -type f \( -name "*.xml" \) | xargs sed -ie "s/Gfx/Gen/g"

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9936>
 2021-04-02 18:33:07 +00:00
Anuj Phogat b75f095bc7 intel: Rename genx keyword to gfxx in source files 
Commands used to do the changes:
export SEARCH_PATH="src/intel src/gallium/drivers/iris src/mesa/drivers/dri/i965"
grep -E "gen[[:digit:]]+" -rIl $SEARCH_PATH | xargs sed -ie "s/gen\([[:digit:]]\+\)/gfx\1/g"

Exclude pack.h and xml changes in this patch:
grep -E "gfx[[:digit:]]+_pack\.h" -rIl $SEARCH_PATH | xargs sed -ie "s/gfx\([[:digit:]]\+_pack\.h\)/gen\1/g"
grep -E "gfx[[:digit:]]+\.xml" -rIl $SEARCH_PATH | xargs sed -ie "s/gfx\([[:digit:]]\+\.xml\)/gen\1/g"

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9936>
 2021-04-02 18:33:07 +00:00
Anuj Phogat 66f6535974 intel: Rename genx keyword to gfxx in build files 
Commands used to do the changes:
export SEARCH_PATH="src/intel src/gallium/drivers/iris src/mesa/drivers/dri/i965"
find $SEARCH_PATH -type f \( -name "*.mk" -o -name "*.sources" -o -name "*.build" \) | xargs sed -ie "s/gen\([[:digit:]]\+\)/gfx\1/g"

Exclude --device-prefix, xml and _pack.h changes in this patch:
find $SEARCH_PATH -type f \( -name "*.mk" -o -name "*.sources" -o -name "*.build" \) | xargs sed -ie "s/gfx\([[:digit:]]\+_pack\.h\)/gen\1/g"
find $SEARCH_PATH -type f \( -name "*.mk" -o -name "*.sources" -o -name "*.build" \) | xargs sed -ie "s/gfx\([[:digit:]]\+\.xml\)/gen\1/g"

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9936>
 2021-04-02 18:33:07 +00:00
Anuj Phogat c1f3a778de intel: Rename GENx prefix in macros to GFXx in source files 
Commands used to do the changes:
export SEARCH_PATH="src/intel src/gallium/drivers/iris src/mesa/drivers/dri/i965"
grep -E "GEN" -rIl src/intel/genxml | grep -E ".*py" |  xargs sed -ie "s/GEN\([%{]\)/GFX\1/g"
grep -E "[^_]GEN[[:digit:]]+" -rIl $SEARCH_PATH | grep -E ".*(\.c|\.h|\.y|\.l)" | xargs sed -ie "s/\([^_]\)GEN\([[:digit:]]\+\)/\1GFX\2/g"

Leave out renaming GFX12_CCS_E macros. They fall under renaming pattern like "_GEN[[:digit:]]+":
grep -E "GFX12_CCS_E" -rIl $SEARCH_PATH | xargs sed -ie "s/GFX12_CCS_E/GEN12_CCS_E/g"

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9936>
 2021-04-02 18:33:07 +00:00
Anuj Phogat 0cfe7e3968 intel: Rename GENx prefix in macros to GFXx in build files 
Commands used to do the changes:
export SEARCH_PATH="src/intel src/gallium/drivers/iris src/mesa/drivers/dri/i965"
grep -E "GEN[[:digit:]]+[[:alpha:]_]*_FILES" -rIl $SEARCH_PATH | xargs sed -ie "s/GEN\([[:digit:]]\+[[:alpha:]_]*_FILES\)/GFX\1/g"

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9936>
 2021-04-02 18:33:07 +00:00
Anuj Phogat dc28390e3c intel: Rename genx keyword in filenames to gfxx 
Commands used to do the changes:
export SEARCH_PATH="src/intel src/gallium/drivers/iris src/mesa/drivers/dri/i965"
find $SEARCH_PATH -type f -name "*gen[[:digit:]]*.*[cph]" -exec sh -c 'f="{}"; mv -- "$f" "${f/gen/gfx}"' \;
grep -E "gen[[:digit:]]+_[[:alnum:]_]*\.(c|h|cpp)" -rIl $SEARCH_PATH | xargs sed -ie "s/gen\([[:digit:]]\+_[[:alnum:]_]*\.\)\(c\|h\|cpp\)/gfx\1\2/g"
grep -E "_gen[[:digit:]]+[[:alnum:]_]*\.(c|h|cpp)" -rIl $SEARCH_PATH | xargs sed -ie "s/\(_\)gen\([[:digit:]]\+[[:alnum:]_]*\.\)\(c\|h\|cpp\)/\1gfx\2\3/g"
grep -E "GEN[[:digit:]]+[[:alnum:]_]*_H( |$)" -rIl $SEARCH_PATH | xargs sed -ie "s/GEN\([[:digit:]]\+[[:alnum:]_]*_H\)\( \|$\)/GFX\1\2/g"

Exclude the "_pack.h" changes:
grep -E "gfx[[:digit:]]+_pack\.h" -rIl $SEARCH_PATH | xargs sed -ie "s/gfx\([[:digit:]]\+_pack\.h\)/gen\1/g"

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9936>
 2021-04-02 18:33:07 +00:00
Anuj Phogat abe9a71a09 intel: Rename gen field in gen_device_info struct to ver 
Commands used to do the changes:
export SEARCH_PATH="src/intel src/gallium/drivers/iris src/mesa/drivers/dri/i965"
grep -E "info\)*(.|->)gen" -rIl $SEARCH_PATH | xargs sed -ie "s/info\()*\)\(\.\|->\)gen/info\1\2ver/g"

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9936>
 2021-04-02 18:33:07 +00:00
Anuj Phogat 99331f6deb intel: Rename genx10 field in gen_device_info struct to verx10 
Commands used to do the changes:
export SEARCH_PATH="src/intel src/gallium/drivers/iris src/mesa/drivers/dri/i965"
grep -E "info\)*(.|->)genx10" -rIl $SEARCH_PATH | xargs sed -ie "s/info\()*\)\(\.\|->\)genx10/info\1\2verx10/g"

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9936>
 2021-04-02 18:33:07 +00:00
Anuj Phogat cc422fa498 intel: Rename ISL_DEV_GEN to ISL_GFX_VER 
Commands used to do the changes:
export SEARCH_PATH="src/intel src/gallium/drivers/iris src/mesa/drivers/dri/i965"
grep -E "ISL_DEV_GEN" -rIl $SEARCH_PATH | xargs sed -ie "s/ISL_DEV_GEN/ISL_GFX_VER/g"

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9936>
 2021-04-02 18:33:07 +00:00
Anuj Phogat 9da8a55b08 intel: Rename GEN_GEN macro to GFX_VER 
Commands used to do the changes:
export SEARCH_PATH="src/intel src/gallium/drivers/iris src/mesa/drivers/dri/i965"
grep -E "GEN_GEN" -rIl $SEARCH_PATH | xargs sed -ie "s/GEN_GEN/GFX_VER/g"

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9936>
 2021-04-02 18:33:06 +00:00
Anuj Phogat 295bb3c263 intel: Rename GEN_VERSIONx10 macro to GFX_VERx10 
Commands used to do the changes:
export SEARCH_PATH="src/intel src/gallium/drivers/iris src/mesa/drivers/dri/i965"
grep -E "GEN_VERSION" -rIl $SEARCH_PATH | xargs sed -ie "s/GEN_VERSION/GFX_VER/g"

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9936>
 2021-04-02 18:33:06 +00:00
Jason Ekstrand d5b56debde anv: Implement VK_EXT_conservative_rasterization 
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4480
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9960>
 2021-04-01 13:34:55 +00:00
Lionel Landwerlin 200e56f84d intel/fs: implement another copy propagation restriction 
We are missing an additional restriction on CHV & upcoming Xe-Hp.

v2: Quote BSW PRMs (Curro)
    Check source is not a scalar (Curro)
    Fix comment (Marcin)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9929>
 2021-04-01 07:48:06 +00:00
Lionel Landwerlin aa53665fda intel/fs/copy_prop: check stride constraints with actual final type 
In some cases we will change the type of the destination register of
an instruction. This is the type we should use to verify that we're
allow to do the replacement.

Otherwise we can hit restrictions on CHV and upcoming Xe-Hp for
instance where the copy propagation transforms this :

send(16) (mlen: 2) vgrf10:UD, 0u, 0u, vgrf35:D, null:UD
mov(16) vgrf11:UW, vgrf10<2>:UW
mov(16) vgrf12:UW, vgrf10+0.2<2>:UW
mov(16) vgrf15:HF, |vgrf11|:HF
mov(16) vgrf16:HF, |vgrf12|:HF
mov(8) vgrf41<2>:UW, vgrf15+0.0:UW group0
mov(8) vgrf42<2>:UW, vgrf15+0.16:UW group8
mov(8) vgrf45<2>:UW, vgrf16+0.0:UW group0
mov(8) vgrf46<2>:UW, vgrf16+0.16:UW group8

into this :

send(16) (mlen: 2) vgrf10:UD, 0u, 0u, vgrf35:D, null:UD
mov(8) vgrf41<2>:HF, |vgrf10+0.0|<2>:HF group0
mov(8) vgrf42<2>:HF, |vgrf10+1.0|<2>:HF group8
mov(8) vgrf45<2>:HF, |vgrf10+0.2|<2>:HF group0
mov(8) vgrf46<2>:HF, |vgrf10+1.2|<2>:HF group8

Because of the floating point use, stride and offets should be the
same.

v2: Fix final destination type selection (Curro)

v3: constify (Curro)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9832>
 2021-03-29 22:14:45 +00:00
Kenneth Graunke d67b343aa0 intel: Mark an otherwise unused variable in intel_dump_gpu as ASSERTED 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9862>
 2021-03-29 20:02:09 +00:00
Tapani Pälli 10cdfce14e intel/common: disable batch decoder on Android platform 
when building with Meson. It requires libexpat that is not available
on Android and we want to avoid it.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9848>
 2021-03-27 19:26:22 +02:00
Lionel Landwerlin 6d72f404df intel/nullhw: fix build 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4507
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9849>
 2021-03-26 20:12:40 +00:00
Iván Briano 042d24971e anv: use helper function to get the buffer size 
This ensures we get a properly aligned size for the buffer so we don't
trip over HW limits for push constants.

Closes #3703
Fixes dEQP-VK.robustness.image_robustness.push.* on HSW

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9699>
 2021-03-25 15:22:20 -07:00
Iván Briano 54b848b245 anv: move buffer size alignment into helper function 
And use ANV_UBO_ALIGNMENT for it instead of a magic number.
This increases the alignment to 64B, but that ought to be good for
everyone.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9699>
 2021-03-25 15:20:53 -07:00
Lionel Landwerlin 8b586d9ed6 intel: Add null hw layer 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2832>
 2021-03-25 19:10:03 +00:00
Jason Ekstrand 82b25a1d75 anv: Align inline uniform data to ANV_UBO_ALIGNMENT 
If we're going to have a #define for UBO alignments, it's probably a
good idea to make sure everything is aligned to that.  This increases
the alignment from 32B to 64B but that shouldn't hurt anyone.

Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9837>
 2021-03-25 19:01:24 +00:00
Kenneth Graunke 5ae276f7e0 intel: Fix release build breakage 
We missed changing one instance of debug_flag to debug_enabled in a
release-only ifdef branch.

Fixes: 758eb18c6f ("intel/compiler: Make vec4 generator take debug_enabled as a parameter")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9839>
 2021-03-25 11:36:58 -07:00
Danylo Piliaiev 2bff8fd53b nir: add nir_shader_as_str function 
It would be later used by Turnip in implementation of
VK_KHR_pipeline_executable_properties.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8877>
 2021-03-25 13:53:33 +00:00
Tapani Pälli 382e5f2737 anv/android: fix image creation with external format 
This fixes crashes seen with following group of tests:
   android.graphics.cts.BasicVulkanGpuTest

Fixes: 6fa56273be ("anv/image: Drop duplicate 'format' in anv_image_create()")
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9799>
 2021-03-25 07:33:38 +02:00
Caio Marcelo de Oliveira Filho e93c8ab023 intel/compiler: Use a struct for brw_compile_cs parameters 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9779>
 2021-03-24 23:18:46 +00:00
Caio Marcelo de Oliveira Filho 05933fb0f7 intel/compiler: Use INTEL_DEBUG=blorp to dump blorp shaders 
Make INTEL_DEBUG=blorp dump the blorp shaders instead using the
general INTEL_DEBUG=fs,vs, which is now reserved to the actual FS and
VS shaders used by the pipeline.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9779>
 2021-03-24 23:18:46 +00:00
Caio Marcelo de Oliveira Filho 7fb1e58651 intel/compiler: Make visitors take debug_enabled as a parameter 
The callers already have this value, and we would like to make it
follow different rules other than stage that might not be visible to
the helper function, so just pass explicitly.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9779>
 2021-03-24 23:18:46 +00:00
Caio Marcelo de Oliveira Filho 758eb18c6f intel/compiler: Make vec4 generator take debug_enabled as a parameter 
The callers already have this value, and we would like to make it
follow different rules other than stage that might not be visible to
the helper function, so just pass explicitly.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9779>
 2021-03-24 23:18:46 +00:00
Caio Marcelo de Oliveira Filho 244d2daa00 intel/compiler: Make brw_postprocess_nir take debug_enabled as a parameter 
The callers already have this value, and we would like to make it
follow different rules other than stage that might not be visible to
the helper function, so just pass explicitly.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9779>
 2021-03-24 23:18:46 +00:00
Caio Marcelo de Oliveira Filho 82d77f0ea8 intel/compiler: Refactor the shader INTEL_DEBUG checks 
Make the check once in a variable, that can be reused for other parts.
Also add `unlikely` to the various conditionals depending on it

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9779>
 2021-03-24 23:18:46 +00:00
Caio Marcelo de Oliveira Filho 57d664245e intel/compiler: Use a struct for brw_compile_vs parameters 
Makes calling code more explicit about what is being set, and allows
take advantage of zero initialization for the ones the callsite don't
care.

Besides moving to the struct, two extra "ergonomic" changes were done:

- Add a new shader_time boolean, so shader_time_index is ignored when
  unused -- this allow taking advantage of the zero initialization of
  unset fields.

- Since we have a struct, provide space for the error_str pointer.
  Both iris and i965 were using it, and the extra rstrdup in case of
  failure shouldn't be a burden for the others.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9779>
 2021-03-24 23:18:46 +00:00
Caio Marcelo de Oliveira Filho f5e1765f98 intel/compiler: Use a struct for brw_compile_fs parameters 
Makes calling code more explicit about what is being set, and allows
take advantage of zero initialization for the ones the callsite don't
care.

Besides moving to the struct, two extra "ergonomic" changes were done:

- Add a new shader_time boolean, so shader_time_index is ignored when
  unused -- this allow taking advantage of the zero initialization of
  unset fields.

- Since we have a struct, provide space for the error_str pointer.
  Both iris and i965 were using it, and the extra rstrdup in case of
  failure shouldn't be a burden for the others.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9779>
 2021-03-24 23:18:46 +00:00
Caio Marcelo de Oliveira Filho 84c3d68344 intel/compiler: Make vue_map parameter const for brw_compile_fs 
Just a documentation hint that the VUE map is not modified.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9779>
 2021-03-24 23:18:46 +00:00