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10573 Commits

Author SHA1 Message Date
Jordan Justen 72e04a6248 intel/gfx7: Change GPGPU Mode to bool 
Suggested-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11564>
 2021-09-30 17:41:33 +00:00
Jordan Justen 90a39cac87 intel/blorp: Emit compute program based on BLORP_BATCH_USE_COMPUTE 
Reworks:
 * Don't pack params, just memcpy param struct (s-b Jason)
 * Old subject: "intel/blorp: Emit compute program if
   params.cs_prog_data is set"
 * Various cleanups of push-const size/alignment (s-b Jason)
 * Fix subslice count by moving to devinfo (s-b Ken)
 * Simplify cw.InterfaceDescriptor code (s-b Ken)
 * Drop some comments from i965 (s-b Ken)

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11564>
 2021-09-30 17:41:33 +00:00
Jason Ekstrand 3e13c4ccf2 anv,iris,genxml: Use NumberOfBarriers on XeHP 
Ref: bspec 55400
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11564>
 2021-09-30 17:41:33 +00:00
Jordan Justen a4c9c242ed blorp: Add blorp_alloc_general_state 
Reworks:
 * Add crocus

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11564>
 2021-09-30 17:41:33 +00:00
Jordan Justen 90feddf38a intel/blorp: Split out surface setup from state emission 
Render will use blorp_setup_binding_table and blorp_emit_btp, but
compute will only use blorp_setup_binding_table.

Rework:
 * Use blorp_setup_binding_table, blorp_emit_btp (s-b Jason)

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11564>
 2021-09-30 17:41:33 +00:00
Jordan Justen b704c9a75b intel/blorp: Split out ps specific sampler state into a separate function 
The compute path will use blorp_emit_sampler_state, whereas the render
path will use blorp_emit_sampler_state_ps.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11564>
 2021-09-30 17:41:33 +00:00
Jordan Justen dbd4934441 intel/blorp: Add blorp_compile_cs 
Reworks:
 * Don't pack params (s-b Jason)
 * Drop nir_remove_dead_variables (s-b Jason)
 * Fix comment s/render target/destination image/ (s-b Ken)

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11564>
 2021-09-30 17:41:33 +00:00
Jordan Justen 998142ea4a intel/blorp: Add subgroup_id input for compute programs 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11564>
 2021-09-30 17:41:33 +00:00
Jordan Justen 51528aeb60 intel/compiler: Use INTEL_DEBUG=blorp to dump blorp compute shaders 
Make INTEL_DEBUG=blorp dump the blorp compute shaders instead using
the general INTEL_DEBUG=cs which is now reserved for actual compute
programs.

Ref: 05933fb0f7 ("intel/compiler: Use INTEL_DEBUG=blorp to dump blorp shaders")
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11564>
 2021-09-30 17:41:33 +00:00
Jordan Justen bd103f9483 intel/blorp: Add brw_blorp_init_cs_prog_key 
Reworks:
 * Split out blorp_init_base_prog_key to share with fs/cs key init (s-b Jason)

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11564>
 2021-09-30 17:41:33 +00:00
Jordan Justen 794a23ddc7 intel/blorp: Add shader_pipeline to brw_blorp_base_key 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11564>
 2021-09-30 17:41:33 +00:00
Jordan Justen 5ace2e36cc intel/blorp: Add compute support to BLORP_CREATE_NIR_INPUT 
Reworks:
 * Set driver_location (s-b Jason)

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11564>
 2021-09-30 17:41:33 +00:00
Jordan Justen a7533a5ad5 intel/blorp: Move most of BLORP_CREATE_NIR_INPUT into a function 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11564>
 2021-09-30 17:41:33 +00:00
Jason Ekstrand 0737b37dcd intel/fs: Emit URB fences when we have LSC 
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Tested-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13092>
 2021-09-29 20:52:54 +00:00
Jason Ekstrand e6a9501aa2 intel/fs: Add the URB fence message 
When they re-arranged all the dataport stuff and added the LSC, doing
URB fencing through the dataport no longer makes sense.  Instead, there
is now a fence message on the URB shared function.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Tested-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13092>
 2021-09-29 20:52:54 +00:00
Jason Ekstrand eb53d82d2d intel/fs: Ignore SLM fences if shared is unused 
Found this nugget while looking at the ACO driver.  It seems sensible to
avoid SLM fences if there is no SLM.  This also makes the check depend
on SLM usage rather than just shader stage which will be useful if we
ever implement task/mesh because task shaders also have SLM.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13092>
 2021-09-29 20:52:54 +00:00
Jason Ekstrand f726246297 intel/fs: Rework fence handling in brw_fs_nir.cpp 
Start off making everything look like LSC where we have three types of
fences: TGM, UGM, and SLM.  Then, emit the actual code in a generation-
aware way.  There are three HW generation cases we care about:
XeHP+ (LSC), ICL-TGL, and IVB-SKL.  Even though it looks like there's a
lot to deduplicate, it only increases the number of ubld.emit() calls
from 5 to 7 and entirely gets rid of the SFID juggling and other
weirdness we've introduced along the way to make those cases "general".
While we're here, also clean up the code for stalling after fences and
clearly document every case where we insert a stall.

There are only three known functional changes from this commit:

 1. We now avoid the render cache fence on IVB if we don't need image
    barriers.

 2. On ICL+, we no longer unconditionally stall on barriers.  We still
    stall if we have more than one to help tie them together but
    independent barriers are independent.  Barrier instructions will
    still operate in write-commit mode and still be scheduling barriers
    but won't necessarily stall.

 3. We now assert-fail for URB fences on LSC platforms.  We'll be adding
    in the new URB fence message for those platforms in a follow-on
    commit.

It is a big enough refactor, however, that other minor changes may be
present.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13092>
 2021-09-29 20:52:54 +00:00
Vinson Lee 77d2bdb0a2 pps: Avoid duplicate elements in with_datasources array. 
Setting -Dperfetto=true and -Ddatasources=intel,panfrost to the
meson command line resulted in duplicate elements.

Fixes: 92180a4376 ("pps: Intel pps driver")
Fixes: 513d1baaea ("pps: Panfrost pps driver")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12379>
 2021-09-29 07:26:18 +00:00
Jason Ekstrand cc9f34cdd6 anv: Switch to common GetDeviceQueues2 and DeviceWaitIdle 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13003>
 2021-09-28 21:08:25 +00:00
Jason Ekstrand 317c5ebf3e anv: Drop anv_queue::flags 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13003>
 2021-09-28 21:08:25 +00:00
Jason Ekstrand b2313b6884 vulkan: Add the pCreateInfo to vk_queue_init() 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13003>
 2021-09-28 21:08:25 +00:00
Mike Blumenkrantz e24ef5d914 anv: assert that legacy_scanout isn't used with explicit modifiers 
these should be mutually exclusive

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12919>
 2021-09-27 17:36:44 -04:00
Caio Marcelo de Oliveira Filho 37f03e89f2 intel: Add and use max_constant_urb_size_kb 
This knowledge was repeated in multiple places so move the values to
intel_device_info struct.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13014>
 2021-09-27 20:51:28 +00:00
Lionel Landwerlin 9d9e67d118 spirv: don't fail on CapabilitySubgroupDispatch if supported 
Since only Anv uses the value, I'm only enabling this on anv.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 518693c3ec ("spirv: Handle the SubgroupSize execution mode")
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13034>
 2021-09-24 20:23:14 +00:00
Yevhenii Kolesnikov dc354b8fda anv: Switch to new debug message helpers 
Signed-off-by: Yevhenii Kolesnikov <yevhenii.kolesnikov@globallogic.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10318>
 2021-09-23 21:14:32 +00:00
Emma Anholt 263072ddaa anv: Use the shared now-in-core feature/prop extension helper functions. 
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12967>
 2021-09-23 16:19:47 +00:00
Yevhenii Kolesnikov 1b085ff03a anv: Use a common vk_queue structure 
Switch to using common structure.

Signed-off-by: Yevhenii Kolesnikov <yevhenii.kolesnikov@globallogic.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13000>
 2021-09-23 15:57:46 +00:00
Yevhenii Kolesnikov c9189f4813 anv: Use a common vk_command_buffer structure 
Switch to using common structure.

Signed-off-by: Yevhenii Kolesnikov <yevhenii.kolesnikov@globallogic.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13000>
 2021-09-23 15:57:46 +00:00
Jordan Justen c746bf4c5c intel/dev: Add display_ver and set adl-p to 13 
Ref: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12908
Cc: mesa-stable
Fixes: e435511b58 ("intel/dev: Add device info for ADL GT2")
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12973>
 2021-09-22 02:32:05 -07:00
Caio Marcelo de Oliveira Filho 47f7b262e1 anv: Refactor subgroup_size_type rules into a single function 
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12946>
 2021-09-21 21:35:20 +00:00
Caio Marcelo de Oliveira Filho 9add809e7f anv: Simplify subgroup_size_type rules for compute shaders 
The populate_base_prog_key will set VARYING depending if the pipeline
flag is used.  Later, when full subgroups flag is set, it will flip to
UNIFORM -- which for compute shaders is effectively the same, so don't
bother setting it again.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12946>
 2021-09-21 21:35:20 +00:00
Christian Gmeiner 3d65cea6ee util/bitset: s/BITSET_SET_RANGE/BITSET_SET_RANGE_INSIDE_WORD 
Prep work for the next commit.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11321>
 2021-09-21 20:25:31 +00:00
Jason Ekstrand 35ac184de0 intel/fs: Handle required subgroup sizes specified in the SPIR-V 
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12959>
 2021-09-21 18:34:59 +00:00
Jordan Justen 99f9075063 Revert "intel/dev: Add display_ver and set adl-p to 13" 
This reverts commit c81acd365e.
 2021-09-21 03:39:31 -07:00
Jordan Justen c81acd365e intel/dev: Add display_ver and set adl-p to 13 
Cc: mesa-stable
Fixes: e435511b58 ("intel/dev: Add device info for ADL GT2")
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12908>
 2021-09-21 02:49:04 -07:00
Ian Romanick 3281ccf4b1 iris: Calculate uses_atomic_load_store after all lowering 
The lowering passes will soon be moved to another function, so there
won't be any choice.

As a side benefit, this allows eliminating the uses_atomic_load_store
**pointer** parameter from brw_nir_lower_storage_image.  For some reason
crocus was passing false instead of NULL.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12858>
 2021-09-17 16:36:08 -07:00
Dave Airlie 929db0a818 intel/decode/gfx6: add support for gfx6 CC/VIEWPORT pointers. 
These have 3 sub states encoded and valid fields on SNB.

Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12864>
 2021-09-16 05:13:16 +10:00
Emma Anholt aed4c0b5a9 nir: Drop the unused instr arg for src/dest copy functions. 
Now that we don't use ralloc, we don't need this arg to get at the right
ralloc ctx.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11776>
 2021-09-14 17:53:06 +00:00
Jordan Justen 333b2185d8 intel/isl: Enable MOCS 61 for external surfaces on TGL 
Reworks:
 * Lionel/Francisco: Add comment

Cc: mesa-stable
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by:  Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12292>
 2021-09-14 05:33:53 +00:00
Anuj Phogat 18477f60e2 intel/dg2: Add L3 configuration 
Rework:
 * Jordan: Merge dg1/dg2 into empty_l3_list

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12711>
 2021-09-14 02:51:03 +00:00
Jordan Justen 4620f8334f intel/dev: Add is_dg2 to devinfo 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12711>
 2021-09-14 02:51:03 +00:00
Jordan Justen c7d8a69249 intel/devinfo: Add devinfo->max_scratch_ids 
This consolidates several duplicated pieces of code into devinfo.
max_scratch_ids is an array that provides the max number of threads
for the rendering and compute stages.

This fixes some exceptions missed by crocus for scratch ids on haswell
and cherryview.

It also fills out devinfo->max_scratch_ids properly for stages VS
through CS on Gfx12.5. But, functionally this should not make a
difference as Gfx12.5 already uses COMPUTE for all stages.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12799>
 2021-09-13 13:26:51 -07:00
Jordan Justen 32e848aeaa intel: Move subslice_total into devinfo 
Reworks:
 * Move asserts for subslice_total into intel_device_info.c (s-b Ken)
 * Drop now unused intel_device_info_subslice_total (s-b Ken)
 * Add comment for subslice_total (Ken)

Suggested-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12799>
 2021-09-13 13:26:23 -07:00
Simon Ser 3c18e69078 vulkan/wsi/x11: add driconf option to not wait under Xwayland 
By default, Mesa's X11 Vulkan WSI will wait for buffers to be ready
before submitting them to Xwayland when the swapchain is created
with the IMMEDIATE mode.

This is undesirable when the Wayland compositor already monitors
fences. A Wayland compositor may want to know the delay between
the buffer submition and the end of the GPU work, this is impossible
to measure if the WSI waits for the buffer to be ready before
submission.

Since most compositors don't monitor fences, let's introduce a driconf
option for this for now. We can reconsider once more compositors
have better support for fences.

Signed-off-by: Simon Ser <contact@emersion.fr>
Acked-by: Michel Dänzer <mdaenzer@redhat.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11290>
 2021-09-13 19:38:13 +00:00
Sagar Ghuge 5f66e5e56d anv: No need to lower to A64 messages for 64-bit atomics 
With LSC support, we can do 64-bit atomics with A32/64 messages.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Suggested-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12566>
 2021-09-09 23:34:33 +00:00
Sagar Ghuge 75e28b8777 intel/compiler: Add support to handle 64-bit atomics with A32 messages 
v1: (Jason)
- Fix parentheses

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12566>
 2021-09-09 23:34:33 +00:00
Sagar Ghuge 9ffd05b41e anv: Advertise support for shaderBufferFloat64AtomicMinMax 
v1:
- Just check has_lsc (Jason)

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12566>
 2021-09-09 23:34:33 +00:00
Sagar Ghuge 527468f56f intel/compiler: Add 64-bit A64 float logical opcode support 
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12566>
 2021-09-09 23:34:33 +00:00
Jason Ekstrand 7f2395046f anv: Advertise support for shaderBufferFloat32AtomicAdd 
Rework: (Sagar)
- Enable shaderBufferFloat32AtomicAdd for XeHPG

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12566>
 2021-09-09 23:34:33 +00:00
Jason Ekstrand 7b21def9c2 intel/fs: Add support for atomic_fadd 
Rework:
- Enable float32 atomic add with LSC (Sagar)
- disassemble new opcode (Caio)

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12566>
 2021-09-09 23:34:33 +00:00