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Author SHA1 Message Date
Marek Olšák 15bc7e1d62 glthread: pack the primitive type to 8 bits 
The maximum valid enum is only 14.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27350>
 2024-02-23 18:03:58 +00:00
Marek Olšák 39edcd695a mesa: deduplicate is_index_type_valid code 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27350>
 2024-02-23 18:03:58 +00:00
Marek Olšák 259a0a9aeb mesa: deduplicate get_index_size_shift code 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27350>
 2024-02-23 18:03:58 +00:00
Marek Olšák 1388be4d39 glthread: pack "size" in Pointer calls as 16 bits 
The only legal values are {1, 2, 3, 4, GL_BGRA}.
We need GLpacked16i to be unsigned, not signed, because GL_BGRA is
greater than 0x8000.

This decreases the size of 1 frame by 10% in Viewperf2020/Catia1.
It decreases the size of many Pointer calls by 8 bytes.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27350>
 2024-02-23 18:03:58 +00:00
Marek Olšák 13a8efcb2c glthread: clean up how vertex stride is packed 
Use a better type name. Also check the function name more accurately
(no change in behavior).

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27350>
 2024-02-23 18:03:58 +00:00
Marek Olšák 617cdedd35 glthread: remove cmd_size from constant-sized calls 
Only variable-sized calls keep cmd_size in their structures, and it's
renamed to num_slots because it's in units of 8-byte elements.

The motivation is to make room for reducing call sizes.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27350>
 2024-02-23 18:03:58 +00:00
Marek Olšák acfefc1f14 glthread: add no_error variants of glDrawArrays* 
The main motivation is that no_error allows us to drop count==0 draws
at the beginning of the marshal function, instead of forwarding them
to the frontend thread. Such draws are plentiful with Viewperf.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27350>
 2024-02-23 18:03:58 +00:00
Marek Olšák 138804fdfc glthread: add no_error variants of glDrawElements* 
The main motivation is that no_error allows us to drop count==0 draws
at the beginning of the marshal function, instead of forwarding them
to the frontend thread. Such draws are plentiful with Viewperf.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27350>
 2024-02-23 18:03:58 +00:00
Marek Olšák c52e1f916a glthread: use _mesa_glthread_fence_call() instead of duplicating that code 
no change in behavior

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27350>
 2024-02-23 18:03:58 +00:00
Marek Olšák 47d589e7d4 glthread: re-enable thread scheduling in st/mesa when glthread is disabled 
This happens when GL_DEBUG_OUTPUT_SYNCHRONOUS is enabled.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27350>
 2024-02-23 18:03:58 +00:00
Chris Rankin c3ceec6cd8 vdpau: Refactor query for video surface formats. 
Cc: mesa-stable

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10614
Signed-off-by: Chris Rankin <rankincj@gmail.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27730>
 2024-02-23 16:26:27 +00:00
Biju Das 174b715391 gallium: Add Renesas rzg2l-du DRM entry point 
RZ/{G2L,G2LC,V2L} SoCs implements an ARM Mali-G31[1]. Add an entry point
for Renesas rzg2l-du DRM vendor, so mesa can be used with it.

[1] https://lore.kernel.org/all/20211208104026.421-3-biju.das.jz@bp.renesas.com/

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27763>
 2024-02-23 15:47:56 +00:00
Karol Herbst d096523af0 rusticl/kernel: make builds private 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27747>
 2024-02-23 14:47:19 +00:00
Karol Herbst 14ccfb41bc rusticl/meson: remove -Aclippy::arc-with-non-send-sync flag 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27747>
 2024-02-23 14:47:19 +00:00
Karol Herbst ce06bdf916 rusticl/icd: verify all cl classes are Send and Sync 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27747>
 2024-02-23 14:47:19 +00:00
Karol Herbst e202903007 rusticl/kernel: make it Send and Sync 
There are a few APIs which don't have to be thread-safe, but we can
optimize it later.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27747>
 2024-02-23 14:47:19 +00:00
Karol Herbst 59cba70751 rusticl/spirv: mark SPIRVBin as Send and Sync 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27747>
 2024-02-23 14:47:19 +00:00
Karol Herbst 17e97a8f06 rusticl/event: make EventSig Send + Sync 
The code was effecitvely that already, but now we can have the compiler
actually verify this.

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27747>
 2024-02-23 14:47:18 +00:00
Karol Herbst a97108d3c7 rusticl/memory: make closures Send and Sync 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27747>
 2024-02-23 14:47:18 +00:00
Karol Herbst aa3b44c02b rusticl/memory: store host_ptr as usize 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27747>
 2024-02-23 14:47:18 +00:00
Karol Herbst 1753b59cfd rusticl/context: complete conversion of SVM pointers to usize 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27747>
 2024-02-23 14:47:18 +00:00
Danylo Piliaiev ebde7d5e87 tu/a7xx: Write even more magic regs to fix rendering issues on Android 
We have to write all the same regs blob is writing or we risk using
stale reg value written by blob.

I went through blob trace again and added all missing magic regs,
I hope for the last time.

This fixes screen corruption for Mobox users and in some cases
for different emulators users. The reg which caused the issue
is HLSQ_UNKNOWN_A9AC.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27721>
 2024-02-23 14:19:11 +00:00
Antonio Gomes 38ffdb883d rusticl/device: Verify for PIPE_CAP_CL_GL_SHARING when enabling gl_sharing 
I think it's better to keep the other checks (check for dmabuf, uuid,
...) as we can use them to know the features required.

Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26071>
 2024-02-23 13:29:00 +00:00
Antonio Gomes d43f9f9c60 radeonsi: Set PIPE_CAP_CL_GL_SHARING to true 
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26071>
 2024-02-23 13:29:00 +00:00
Antonio Gomes 6e7d1725a3 iris: Set PIPE_CAP_CL_GL_SHARING to true 
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26071>
 2024-02-23 13:29:00 +00:00
Antonio Gomes 12f1a4c311 gallium: Add new PIPE_CAP_CL_GL_SHARING 
We have a situation where some drivers have all the required features,
but they are not working with gl_sharing, so we end up advertising it
wrongly. Add this cap to ensure this driver was tested to work with
cl_khr_gl_sharing.

Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26071>
 2024-02-23 13:29:00 +00:00
Antonio Gomes 50f6478e3d rusticl/gl: Bump mesa_glinterop_device_info to version 4 
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26071>
 2024-02-23 13:29:00 +00:00
Antonio Gomes a7272a6f24 mesa/st: Skip querying PCI values in interop_query_device_info if version >= 4 
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26071>
 2024-02-23 13:29:00 +00:00
Oskar Viljasaar 89622f5089 tu: Use common physical device properties infrastructure 
Use the same intializing trick as in 27d5543: first we initialize our
properties struct to { false }, then we fill the fields in one by one.
C++ does not allow assigning to an array from an initializer list, so
the properties exposed as an array in the struct are initialized either
one by one, or assigned in a chain.
As the properties are initialized at init time, move tu_get_properties
and tu_get_physical_device_properties_* before tu_physical_device_init,
so get_properties() would be callable by it.

This lets us delegate the physical device property entrypoints to
common runtime code.

Tested with drm-shim, doing a diff on vulkaninfo output. Differing
fields were pipelineCacheUUID, driverInfo and driverUUID, i.e. the
actual properties do not differ.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27723>
 2024-02-23 13:03:03 +00:00
Danylo Piliaiev f4c40fc89c tu: Add workaround for D3D11 games accessing UBO out of bounds 
Some D3D11 games rely on out-of-bounds indirect UBO loads to return
real values from underlying bound descriptor. This workaround would
prevent us from lowering indirectly accessed UBOs to consts.

Later DXVK would declare dynamically indexed uniforms with upper
size bound, to make the accesses spec compliant. But for now
we need our own workaround.

Known affected games:
- Dark Souls 3
- Sekiro: Shadows Die Twice
- Final Fantasy Type-0 HD
- Ultrakill
- Dishonored 2

DXVK discussions:
- https://github.com/doitsujin/dxvk/issues/405
- https://github.com/doitsujin/dxvk/issues/3861

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27727>
 2024-02-23 12:08:53 +00:00
Michel Dänzer 7a6836611e egl/wayland: Flush after blitting to linear copy 
We need to flush after blitting to the linear copy, or the Wayland
compositor may not see the correct linear buffer contents.

v2:
* Keep blitImage call in the same place (Daniel Stone)
* Add second flush for the blit to linear copy

Fixes: 58f90fd03f ("egl/wayland: fix glthread crashes")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9816
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27718>
 2024-02-23 08:43:54 +00:00
Faith Ekstrand f890b515ef nvk: Don't use WAIT_AVAILABLE in nvk_upload_queue_sync 
This was a copy+paste error, probably from vk_drm_syncobj.c.  If we do
WAIT_AVAILABLE, it only waits for the dma_fence to exist, not for it to
signal.  Instead, we want WAIT_FOR_SUBMIT.  (Technically, that's not
necessary but it is typical for CPU waits to also wait for the time
point to materialize.)

Fixes: 2074e28a0d ("nvk: Add an upload queue")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27757>
 2024-02-23 03:31:57 +00:00
Joshua Ashton 6767ad9c86 meson: Enable d3d12 in gallium_drivers by default on Windows 
This is pretty much the only usable one that isn't
swrast for some people, eg. WoA + QCom.

Signed-off-by: Joshua Ashton <joshua@froggi.es>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27737>
 2024-02-23 02:28:29 +00:00
Joshua Ashton 5a6de45bd5 meson: Enable zink in gallium_drivers by default 
Zink is the only way to use hw accelerated GL on
a7xx and the preferred way for hw supporting NVK.

Start building Zink by default everywhere that we
would build swrast by default, except for Mac +
Cygwin + Haiku.

Signed-off-by: Joshua Ashton <joshua@froggi.es>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27737>
 2024-02-23 02:28:29 +00:00
Karol Herbst 2b9c0e3768 zink: lower unaligned memory accesses 
Fixes `vload_half` in OpenCL

Fixes: 0288cb0a0c ("zink: lower vec8/16")
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27754>
 2024-02-23 00:26:56 +00:00
Benjamin Lee 944ef1771e nvk: disable shaderResourceMinLod on pre-sm70 
The hardware's TEX instruction doesn't support this when using indirect
texture access, which we're currently using for everything.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27733>
 2024-02-22 21:17:17 +00:00
Benjamin Lee a7166386db nak: fix tex offset encoding on SM50 
It should be bit 36, not bit 54. Bit 54 probably came from the direct
variant.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27733>
 2024-02-22 21:17:16 +00:00
Benjamin Lee 59d6645c6b nak: fix lod mode encoding for SM50 tld op 
The bit flag was backwards, set=ll and cleared=lz. This fixes
dEQP-VK.glsl.texture_functions.texelfetch.* from the CTS.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27733>
 2024-02-22 21:17:16 +00:00
Charlie Turner 639a9a1c05 amd, radeonsi: Lower minimum supported video dimensions for AV1 
For AV1, the hardware supports decoding at 16x16, but for AVC & HEVC,
64 is the minimum.

The following Fluster tests used to check this,

av1-1-b8-01-size-16x16.ivf
av1-1-b8-01-size-32x32.ivf

Signed-off-by: Charlie Turner <cturner@igalia.com>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27085>
 2024-02-22 19:49:28 +00:00
Konstantin Seurer d95c30b6ec ac/parese_ib: Handle more packets 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27451>
 2024-02-22 19:25:39 +00:00
Konstantin Seurer ebbbca005e ac/parse_ib: Handle 32bit PKT3_DISPATCH_INDIRECT addrs 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27451>
 2024-02-22 19:25:39 +00:00
Konstantin Seurer fea21e5649 ac/parse_ib: Annotate addresses with UAF/OOB info 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27451>
 2024-02-22 19:25:39 +00:00
Konstantin Seurer badd2131b5 ac/parse_ib: Dump the ADDR field of PKT3_SET_BASE 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27451>
 2024-02-22 19:25:39 +00:00
Konstantin Seurer 160d18b273 ac/parse_ib: Add and use print_addr 
Writes the whole address on one line.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27451>
 2024-02-22 19:25:39 +00:00
Mike Blumenkrantz dfe331930c zink: don't destroy the current batch state on context destroy 
these are owned by the screen now

should fix some flakiness with shared contexts

Fixes: b06f6e00fb ("zink: fix heap-use-after-free on batch_state with sub-allocated pipe_resources")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27749>
 2024-02-22 19:04:09 +00:00
Mark Janes dd0f6d70ba pan/va: Add missing valhall_enums dep to bifrost_tests 
bifrost_tests compilation fails if the valhall_enums.h has not been
generated.

Acked-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27738>
 2024-02-22 18:43:37 +00:00
Louis-Francis Ratté-Boulianne 439fce0c17 panfrost: Add AFBC packing support for RG formats 
Only a matter of enabling it as packing itself works the same no
matter the number of components.

Signed-off-by: Louis-Francis Ratté-Boulianne <lfrb@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27471>
 2024-02-22 18:23:51 +00:00
Sagar Ghuge c3244135fa anv: Set timestampValidBits to 64bits 
On Xe2+, timestamp register can hold value upto 64-bit.

This change also fixes the timestamp related tests on Xe2 platform.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27713>
 2024-02-22 17:58:38 +00:00
Samuel Pitoiset 3004923ae3 radv: add support for conditional rendering on the compute queue with DGC 
Conditional rendering is annoying to implement on ACE because there is
no predication packet like on GFX. With DGC it's even worse because
ACE is missing the IB2 packet which means it's not possible to predicate
the DGC IB entirely.

The provided solution is to always run the DGC prepare shader if
conditional rendering is enabled in order to generate a cmdbuf which
only contains NOPs.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27673>
 2024-02-22 17:32:58 +00:00
Samuel Pitoiset f843027c22 radv: store/reset conditional rendering user info in the helpers 
This also correctly initialize predication_op when the hw doesn't
support 32-bit predicate.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27673>
 2024-02-22 17:32:58 +00:00