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tu/a7xx: Write even more magic regs to fix rendering issues on Android

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We have to write all the same regs blob is writing or we risk using
stale reg value written by blob.

I went through blob trace again and added all missing magic regs,
I hope for the last time.

This fixes screen corruption for Mobox users and in some cases
for different emulators users. The reg which caused the issue
is HLSQ_UNKNOWN_A9AC.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27721>
This commit is contained in:
Danylo Piliaiev
2024-02-21 13:33:43 +01:00
committed by Marge Bot
parent 38ffdb883d
commit ebde7d5e87
2 changed files with 39 additions and 9 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/freedreno/common/freedreno_devices.py
+30
View File
@@ -851,6 +851,16 @@ a730_raw_magic_regs = [
[A6XXRegs.REG_A7XX_GRAS_UNKNOWN_80A7, 0x00000000],
[A6XXRegs.REG_A7XX_GRAS_UNKNOWN_810B, 0x3],
[A6XXRegs.REG_A7XX_HLSQ_UNKNOWN_A9AC, 0x00000000],
[A6XXRegs.REG_A7XX_RB_UNKNOWN_8E79, 0x00000000],
[A6XXRegs.REG_A7XX_RB_UNKNOWN_8899, 0x00000000],
[A6XXRegs.REG_A7XX_RB_UNKNOWN_88F5, 0x00000000],
# Shading rate group
[A6XXRegs.REG_A6XX_RB_UNKNOWN_88F4, 0x00000000],
[A6XXRegs.REG_A7XX_HLSQ_UNKNOWN_A9AD, 0x00000000],
[A6XXRegs.REG_A7XX_GRAS_UNKNOWN_80F4, 0x00000000],
]
add_gpus([
@@ -960,6 +970,16 @@ add_gpus([
[A6XXRegs.REG_A7XX_GRAS_UNKNOWN_80A7, 0x00000000],
[A6XXRegs.REG_A7XX_GRAS_UNKNOWN_810B, 0x3],
[A6XXRegs.REG_A7XX_HLSQ_UNKNOWN_A9AC, 0x00000000],
[A6XXRegs.REG_A7XX_RB_UNKNOWN_8E79, 0x00000000],
[A6XXRegs.REG_A7XX_RB_UNKNOWN_8899, 0x00000000],
[A6XXRegs.REG_A7XX_RB_UNKNOWN_88F5, 0x00000000],
# Shading rate group
[A6XXRegs.REG_A6XX_RB_UNKNOWN_88F4, 0x00000000],
[A6XXRegs.REG_A7XX_HLSQ_UNKNOWN_A9AD, 0x00000000],
[A6XXRegs.REG_A7XX_GRAS_UNKNOWN_80F4, 0x00000000],
],
))
@@ -1026,6 +1046,16 @@ add_gpus([
[A6XXRegs.REG_A7XX_GRAS_UNKNOWN_80A7, 0x00000000],
[A6XXRegs.REG_A7XX_GRAS_UNKNOWN_810B, 0x3],
[A6XXRegs.REG_A7XX_HLSQ_UNKNOWN_A9AC, 0x00000000],
[A6XXRegs.REG_A7XX_RB_UNKNOWN_8E79, 0x00000000],
[A6XXRegs.REG_A7XX_RB_UNKNOWN_8899, 0x00000000],
[A6XXRegs.REG_A7XX_RB_UNKNOWN_88F5, 0x00000000],
# Shading rate group
[A6XXRegs.REG_A6XX_RB_UNKNOWN_88F4, 0x00000000],
[A6XXRegs.REG_A7XX_HLSQ_UNKNOWN_A9AD, 0x00000000],
[A6XXRegs.REG_A7XX_GRAS_UNKNOWN_80F4, 0x00000000],
[0x930a, 0],
[0x960a, 1],
[A6XXRegs.REG_A7XX_SP_PS_ALIASED_COMPONENTS_CONTROL, 0],
src/freedreno/registers/adreno/a6xx.xml
+9 -9
View File
@@ -1996,7 +1996,7 @@ to upconvert to 32b float internally?
<!-- Something connected to depth-stencil attachment size -->
<reg32 offset="0x8007" name="GRAS_UNKNOWN_8007" variants="A7XX-" usage="rp_blit"/>
<reg32 offset="0x8008" name="GRAS_UNKNOWN_8008" variants="A7XX-" usage="rp_blit"/>
<reg32 offset="0x8008" name="GRAS_UNKNOWN_8008" variants="A7XX-" usage="cmd"/>
<reg32 offset="0x8009" name="GRAS_UNKNOWN_8009" variants="A7XX-" usage="cmd"/>
<reg32 offset="0x800a" name="GRAS_UNKNOWN_800A" variants="A7XX-" usage="cmd"/>
@@ -2211,12 +2211,12 @@ to upconvert to 32b float internally?
<reg32 offset="0x80f1" name="GRAS_SC_WINDOW_SCISSOR_BR" type="a6xx_reg_xy" usage="rp_blit"/>
<!-- 0x80f4 - 0x80fa are used for VK_KHR_fragment_shading_rate -->
<reg64 offset="0x80f4" name="GRAS_UNKNOWN_80F4" variants="A7XX-"/>
<reg64 offset="0x80f5" name="GRAS_UNKNOWN_80F5" variants="A7XX-"/>
<reg64 offset="0x80f6" name="GRAS_UNKNOWN_80F6" variants="A7XX-"/>
<reg64 offset="0x80f8" name="GRAS_UNKNOWN_80F8" variants="A7XX-"/>
<reg64 offset="0x80f9" name="GRAS_UNKNOWN_80F9" variants="A7XX-"/>
<reg64 offset="0x80fa" name="GRAS_UNKNOWN_80FA" variants="A7XX-"/>
<reg64 offset="0x80f4" name="GRAS_UNKNOWN_80F4" variants="A7XX-" usage="cmd"/>
<reg64 offset="0x80f5" name="GRAS_UNKNOWN_80F5" variants="A7XX-" usage="cmd"/>
<reg64 offset="0x80f6" name="GRAS_UNKNOWN_80F6" variants="A7XX-" usage="cmd"/>
<reg64 offset="0x80f8" name="GRAS_UNKNOWN_80F8" variants="A7XX-" usage="cmd"/>
<reg64 offset="0x80f9" name="GRAS_UNKNOWN_80F9" variants="A7XX-" usage="cmd"/>
<reg64 offset="0x80fa" name="GRAS_UNKNOWN_80FA" variants="A7XX-" usage="cmd"/>
<enum name="a6xx_lrz_dir_status">
<value value="0x1" name="LRZ_DIR_LE"/>
@@ -4329,10 +4329,10 @@ to upconvert to 32b float internally?
</reg32>
<!-- Always 0 -->
<reg32 offset="0xa9ac" name="HLSQ_UNKNOWN_A9AC" variants="A7XX-"/>
<reg32 offset="0xa9ac" name="HLSQ_UNKNOWN_A9AC" variants="A7XX-" usage="cmd"/>
<!-- Used in VK_KHR_fragment_shading_rate -->
<reg32 offset="0xa9ad" name="HLSQ_UNKNOWN_A9AD" variants="A7XX-"/>
<reg32 offset="0xa9ad" name="HLSQ_UNKNOWN_A9AD" variants="A7XX-" usage="cmd"/>
<reg32 offset="0xa9ae" name="HLSQ_UNKNOWN_A9AE" variants="A7XX-" usage="rp_blit">
<bitfield name="SYSVAL_REGS_COUNT" low="0" high="7" type="uint"/>