Commit Graph

186467 Commits

Author SHA1 Message Date
Marek Olšák
ad44d7eba0 radeonsi: reorder NIR passes in get_nir_shader (part 1)
Put passes that optimize the code first, and passes that lower it later.
This will be needed later.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32910>
2025-01-29 07:19:47 +00:00
Marek Olšák
5c874f5930 radeonsi: cosmetic changes in get_nir_shader
si_init_gs_output_info is moved later and is already memset

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32910>
2025-01-29 07:19:46 +00:00
Marek Olšák
f05021dd2f radeonsi: simplify how the NIR name of shader variants is modified
we don't need to restore the original name

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32910>
2025-01-29 07:19:46 +00:00
Marek Olšák
36e3f6d9bf radeonsi: set the "first" parameter of si_nir_opts correctly
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32910>
2025-01-29 07:19:45 +00:00
Marek Olšák
e23ccb6c46 radeonsi: call si_nir_late_opts unconditionally
We always have progress==true (e.g. due to si_nir_lower_abi), so late_opts
is likely to be always true.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32910>
2025-01-29 07:19:45 +00:00
Marek Olšák
58c91fb8cf radeonsi: add si_nir_shader_ctx holding parameters from si_get_nir_shader
we'll need to pass this structure around

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32910>
2025-01-29 07:19:44 +00:00
Marek Olšák
3d1886f6c7 radeonsi: call si_init_gs_output_info in si_get_nir_shader
some code reordering is needed

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32910>
2025-01-29 07:19:44 +00:00
Marek Olšák
d580313929 radeonsi: add load_polygon_stipple_buffer_amd instead of using si_shader_args
We will lower polygon stipple before we have si_shader_args, so we need
an intrinsic to get the buffer descriptor.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32910>
2025-01-29 07:19:43 +00:00
Marek Olšák
cd3079a1ea radeonsi: remove si_nir_kill_ps_outputs and use ac_nir_lower_ps_early instead
ac_nir_lower_ps_early does the same thing better.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32910>
2025-01-29 07:19:42 +00:00
Marek Olšák
c5d8100d10 radeonsi: use load_pixel_coord for polygon stipple lowering
We will get shader_info from NIR after this and before si_init_shader_args,
so we need to use system values.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32910>
2025-01-29 07:19:42 +00:00
Marek Olšák
f156abd2a7 radeonsi: simplify how broadcast_last_cbuf is implemented for PS epilogs
We don't need to look at the framebuffer state and record how many color
buffers to write. Instead, we can deduce which color buffers are enabled
from spi_shader_col_format, which already does the right thing.

So PS epilogs only need a single bool flag that determines whether all
enabled color buffers should be written.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32910>
2025-01-29 07:19:41 +00:00
Marek Olšák
28e9fca134 radeonsi: don't set the alpha ref user SGPR if alpha test doesn't use it
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32910>
2025-01-29 07:19:41 +00:00
Marek Olšák
3dcbf743c4 radeonsi: implement replacing frag_coord with pixel_coord at draw time
This adds an option into the prolog key to replace frag_coord.xy with
pixel_coord when sample shading is disabled, which is most of the time.
This reduces the number of input VGPRs.

It's already implement in ac_nir_lower_ps_early for monolithic shaders
and the PS prolog in ACO, so this just implements it for the PS prolog
in LLVM IR.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32910>
2025-01-29 07:19:40 +00:00
Marek Olšák
8e8eda4089 radeonsi: fix PS prolog not counting used fragcoord VGPRs correctly
Using the used component count is not enough. We need to consider
the component mask because any component can be disabled. This might
fix tests.

This removes the component counting from ac_get_fs_input_vgpr_cnt
and determines the component mask where it's needed.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32910>
2025-01-29 07:19:40 +00:00
Marek Olšák
67c772c293 radeonsi: get sample positions from user SGPRs instead of memory
This should be faster.

2 user SGPRs contain 8 sample positions, storing 4 bits per coordinate
and extracting them in the shader.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32910>
2025-01-29 07:19:39 +00:00
Marek Olšák
b3fc49686e ac/nir: clamp vertex color outputs in the right place
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32910>
2025-01-29 07:19:38 +00:00
Marek Olšák
3b78dcec05 radeonsi: disallow compute queues on Raven/Raven2 due to hangs
Fixes: 58b512ddd6 - radeonsi: execute clears at resource allocation using compute instead of gfx
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12310

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33248>
2025-01-29 06:49:43 +00:00
Marek Olšák
30211d0f4a mesa: enable GL name reuse for virgl
I think we only have to disable it for Qemu.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33156>
2025-01-29 06:22:42 +00:00
Friedrich Vock
50e6e3e4ad nir: Add indirect call optimizations
Acked-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29577>
2025-01-29 04:38:51 +00:00
Friedrich Vock
ebbb18aeb6 nir: Free liveness info when invalidating metadata
Liveness info can be huge, since with larger shaders it essentially
grows quadratically (linear increase in number of SSA defs *
linear increase in blocks).

Freeing liveness info early helps somewhat mitigate memory usage here.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29577>
2025-01-29 04:38:51 +00:00
Friedrich Vock
9b1f31a615 nir: Add nir_instr_is_before helper
is_instr_between works similarly but requires special-casing w.r.t
the first instruction in a block for the same effect.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29577>
2025-01-29 04:38:51 +00:00
Friedrich Vock
a8ce60eec1 nir: Apply passes to all functions
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29577>
2025-01-29 04:38:51 +00:00
Friedrich Vock
bb40284f76 nir: Add indirect calls
Used to jump to a function referred to by a runtime pointer.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29577>
2025-01-29 04:38:51 +00:00
Friedrich Vock
4432cf0a58 vtn: Set parameter type in glsl_type_add_to_function_params
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29577>
2025-01-29 04:38:51 +00:00
Friedrich Vock
26cbb6b933 nir: Add parameter divergence info
Indirect calls may have non-divergent parameters that need to be
explicitly marked as such.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29577>
2025-01-29 04:38:51 +00:00
Valentine Burley
7df869b7c9 zink/ci: Update checksum for Osmos trace on TGL
The checksum for the Osmos trace on TGL has changed, so update it
to reflect the current state of the trace.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Reviewed-by: Mike Blumenkrantz <None>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33256>
2025-01-29 04:16:26 +00:00
Valentine Burley
7d66facfda ci: Skip broken PenumbraOverture trace for zink and freedreno
This trace contains generated GL IDs from the time it was recorded,
making it invalid.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Reviewed-by: Mike Blumenkrantz <None>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33256>
2025-01-29 04:16:25 +00:00
Daniel Stone
101065642d ci/debian: Upgrade Debian images to LLVM 19
LLVM 15 is pretty old, and notably not supported by either ANGLE nor
Skia anymore. So let's move up to LLVM 19 using packages provided by
LLVM themselves, apart from PPC and ARMv7 which don't have builds.

The Skia build now requires a bunch of new warning exclusions; hopefully
most of these are no longer needed when we can upgrade Skia shortly.

The ci-deb-repo revision has also been bumped to get us a new version of
xtensor which builds with LLVM 19, and a version of spirv-tools which
also works with LLVM 19.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Closes: mesa/mesa#11538
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33137>
2025-01-29 03:23:28 +00:00
Daniel Stone
87809f6236 pipe_loader: Fix pipe_i915 with the dynamic loader
When building for the dynamic loader used by e.g. Clover, pipe_i915 was
the only target failing to declare a driver descriptor. This becomes an
error with more aggressive linkers.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Fixes: 87392385b5 ("gallium/drm: Define the DRM entrypoints in drm_helper.h")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33137>
2025-01-29 03:23:27 +00:00
David Tobolik
49b20a88db rusticl/style: add util for conversion with err
NEW util/conversion.rs

Adds traits `TryFromWithErr` and `TryIntoWithErr` and their
implementation for types with `TryFrom` and `TryInto` traits

former
```
try_into().map_err(|_| CL_OUT_OF_HOST_MEMORY)
try_from(val).map_err(|_| CL_OUT_OF_HOST_MEMORY)
```
can now be written as
```
try_into_with_err(CL_OUT_OF_HOST_MEMORY)
try_from_with_err(val, CL_OUT_OF_HOST_MEMORY)
```

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33267>
2025-01-29 02:51:21 +00:00
David Tobolik
98f0f6594a rusticl/style: use Arc::clone instead of .clone()
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33267>
2025-01-29 02:51:21 +00:00
Job Noorman
f577118fe1 ir3/a7xx: enable delayed src2 read for all cat3 instructions
cat3 instructions read their 3rd src later than their first two srcs.
Pre-a7xx, this was only supported for mad(sh) but on a7xx, it works for
all cat3 instructions.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33183>
2025-01-29 02:19:50 +00:00
Job Noorman
992a6cc050 ir3/a7xx: update delays slots
The delay slots on a7xx are:
- ALU to ALU: 2
- Non-ALU: 5
- cat3 src2 read: 1

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33183>
2025-01-29 02:19:50 +00:00
Job Noorman
5460be5d33 ir3: make delay slots a compiler property
They changed on a7xx so we want to make it configurable.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33183>
2025-01-29 02:19:50 +00:00
Job Noorman
2c7c62dfd9 ir3: add helper to calculate src read delay
cat3 instructions read their 3rd src later than their first two srcs.
This was implemented in two different places: once for scheduling and
once for legalization. Extract this logic in a new helper and also add
similar logic for gat/swz there (which the scheduling logic failed to
account for).

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33183>
2025-01-29 02:19:50 +00:00
Job Noorman
e7ac1094f6 ir3: rematerialize preamble defs in block dominated by sources
Preamble defs were rematerialized at the end of the preamble. However,
when some of the sources were defined inside control flow, this would
lead to these sources not dominating their use. Fix this by finding the
block that is dominated by all sources and inserting the new instruction
there.

Also make sure we only de-duplicate instructions if the new instruction
is dominated by the existing one.

Fixes a NIR validation error in Devil may cry 5.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Fixes: fdfe86aa52 ("ir3: Expand preamble rematerialization")
Fixes: 6a744ddebc ("ir3: Initial support for pushing globals with ldg.k")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33270>
2025-01-29 01:45:59 +00:00
Connor Abbott
5f3cad0026 tu: Add missing assignment to shared_viewport
This was accidentally deleted when rewriting to use common Vulkan
dynamic state. This meant we wouldn't correctly fall back when someone
accidentally used FDM together with multiple viewports.

Fixes: 97da0a7734 ("tu: Rewrite to use common Vulkan dynamic state")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33241>
2025-01-29 01:17:48 +00:00
Job Noorman
1adf2c9d7c ir3: schedule alias.rt at the end of the preamble
Scheduling an alias.rt right before an alias.tex causes a GPU hang.
Follow the blob and schedule all alias.rt at the end of the preamble to
prevent this from happening.

Fixes a hang in Borderlands 3 on medium or higher graphics settings.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Fixes: 0aa9678d4d ("ir3: add support for alias.rt")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33238>
2025-01-29 00:46:22 +00:00
Alyssa Rosenzweig
3bfcc4f323 clc,libagx: automatically set lang version
bit less meson cargocult.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33242>
2025-01-28 23:01:32 +00:00
Alyssa Rosenzweig
9f460eadab clc,libagx: drop --in for mesa_clc
just accept the arguments as-is. this matches how gcc/clang actually work
and simplifies the meson.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33242>
2025-01-28 23:01:32 +00:00
Alyssa Rosenzweig
164a161279 meson: project-wide fs = import('fs')
reduces a bit of boilerplate.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33242>
2025-01-28 23:01:32 +00:00
Corentin Noël
61626296f2 virgl/ci: Re-enable virgl-traces
This reverts commit 3a7737ffb5

Signed-off-by: Corentin Noël <corentin.noel@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33265>
2025-01-28 21:07:09 +00:00
Samuel Pitoiset
18c7eafcdc radv: fix programming mip level for TILED_SUB_WINDOWS on GFX12
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33252>
2025-01-28 20:32:11 +00:00
Samuel Pitoiset
7c949f1760 radv: fix programming pitches for LINEAR_SUB_WINDOW on GFX12
GFX12 supports up to 64k images.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33252>
2025-01-28 20:32:11 +00:00
Ruijing Dong
1a942f53cc radeonsi/vcn: center mv map buffer changed in vcn5.x
center mv map buffer size changed on vcn5.x, please be aware
that vcn5.0 will not enable 2pass untill vcn5.x.

Reviewed-by: David Rosca <david.rosca@amd.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33215>
2025-01-28 19:50:16 +00:00
Lucas De Marchi
1bd6a2efe1 intel/tools: Fix Xe KMD error dump parser
Xe KMD originally put the exec queue snapshot in the wrong topic,
XE_TOPIC_GUC_CT. Add it to the right one while still keeping a fallback
to the previous place so the new version of the tool is able to parse
both before and after the kernel change.

Based on previous version by José Roberto de Souza <jose.souza@intel.com>
at https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32617

Cc: stable
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33177>
2025-01-28 19:11:26 +00:00
Pavel Ondračka
220590f41a r300: fix memory leak in contant remaping
Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Reviewed-by: Filip Gawin <None>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33066>
2025-01-28 17:42:53 +00:00
Pavel Ondračka
f00f08c02d r300: remove support for register arrays from nir_to_rc
Backend can't handle it and no app which we can reasonably run uses
this anyway AFAIK.

Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Reviewed-by: Filip Gawin <None>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33066>
2025-01-28 17:42:53 +00:00
Pavel Ondračka
89c06ea0f6 r300: get rid of some texture fixups
Textures opcodes can't read from the contant registers, however we can
just handle this fine in the native swizzle pass. Others like saturate
for tex instructions) can't happen anyway since we swithed to nir_to_tgsi
long time ago. However, keep the asserts just to be safe.

Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Reviewed-by: Filip Gawin <None>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33066>
2025-01-28 17:42:53 +00:00
Pavel Ondračka
47207dcb0b r300: get rid of the register rename pass
The pass tried to convert shaders to a SSA-like form. However since
we no longer allocate registers in NIR, and we try hard to keep the
SSA-like form during the later passes, this is now superfluous.

Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Reviewed-by: Filip Gawin <None>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33066>
2025-01-28 17:42:53 +00:00