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Author SHA1 Message Date
Chan, Roy 08fd9aab30 amd/vpelib: fix memory corruption 
[WHY]
Wrong structure size being allocated

[HOW]
fixed the structure size during allocation

Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
Acked-by: Chuanyu Tseng <Chuanyu.Tseng@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36433>
 2025-07-29 09:17:25 +00:00
Nagulendran, Iswara 74c88f740f amd/vpelib: Fix Issues with Background Color insertions 
[WHY]
Background Color Insertion, test cases involving studio output fails

[HOW]
Move background color convertion into revision specific resource
files and isolated what needed to be executed for VPE

Reviewed-by: Jesse Agate <Jesse.Agate@amd.com>
Reviewed-by: Roy Chan <Roy.Chan@amd.com>
Acked-by: Chuanyu Tseng <Chuanyu.Tseng@amd.com>
Signed-off-by: Iswara Nagulendran <Iswara.Nagulendran@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36433>
 2025-07-29 09:17:25 +00:00
Assadian, Navid b529d38ae9 amd/vpelib: Exit when VPE not support in debug 
When the debug flag is set to assert when vpe is not supported, instead
of assert it is preferable to exit so the CI aborts the process instead
of waiting on the assert message.

[WHY]
In debug mode for CI, when assert the process doesn't abort and the CI
terminates on time out.

[HOW]
Using exit instead of assert

Reviewed-by: Jesse Agate <Jesse.Agate@amd.com>
Reviewed-by: Roy Chan <Roy.Chan@amd.com>
Acked-by: Chuanyu Tseng <Chuanyu.Tseng@amd.com>
Signed-off-by: Navid Assadian <navid.assadian@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36433>
 2025-07-29 09:17:24 +00:00
Kovac, Krunoslav 5b8b5c4c49 amd/vpelib: Fix Possible dereferencing null 
pointer issue

[WHY]
Mostly dereferencing possible null ptrs

[HOW]
Add checks / refactor code.

Reviewed-by: Roy Chan <Roy.Chan@amd.com>
Reviewed-by: Jesse Agate <Jesse.Agate@amd.com>
Acked-by: Chuanyu Tseng <Chuanyu.Tseng@amd.com>
Signed-off-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36433>
 2025-07-29 09:17:24 +00:00
Chang, Tomson 48495c142a amd/vpelib: Add missing swizzle and dcc info 
Add missing swizzle mode and dcc info

Reviewed-by: Ricky Lin <Ricky.Lin@amd.com>
Reviewed-by: Jude Shih <Jude.Shih@amd.com>
Acked-by: Chuanyu Tseng <Chuanyu.Tseng@amd.com>
Signed-off-by: Tomson Chang <tomson.chang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36433>
 2025-07-29 09:17:24 +00:00
Hsieh, Mike d281a5587d amd/vpelib: add max/min input output capability 
[WHY]
Capability need to show max and min input/output size.

[HOW]
Add max_input_size, max_ouptut_size, min_output_size and min_imput_size.

Reviewed-by: Roy Chan <Roy.Chan@amd.com>
Reviewed-by: Ricky Lin <Ricky.Lin@amd.com>
Acked-by: Chuanyu Tseng <Chuanyu.Tseng@amd.com>
Signed-off-by: Mike Hsieh <Mike.Hsieh@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36433>
 2025-07-29 09:17:24 +00:00
Hsieh, Mike 6b279abcac amd/vpelib: bug fix: remove unnecessary free 
[WHY]
vpe_priv.resource should not be freed when destroy resource

[HOW]
Remove unnecessary free.

Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
Reviewed-by: Brendan Steve Leder <BrendanSteven.Leder@amd.com>
Acked-by: Chuanyu Tseng <Chuanyu.Tseng@amd.com>
Signed-off-by: Mike Hsieh <Mike.Hsieh@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36433>
 2025-07-29 09:17:24 +00:00
Hsieh, Mike e1ff093e63 amd/vpelib: add format, colorspace check function 
[WHY]
VPE does not support pixel format and colorspace support check.

[HOW]
add vpe_create_engine function to support stateless API.
Add new function to support pixel format check and colorspace support
check.

Reviewed-by: Roy Chan <Roy.Chan@amd.com>
Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
Acked-by: Chuanyu Tseng <Chuanyu.Tseng@amd.com>
Signed-off-by: Mike Hsieh <Mike.Hsieh@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36433>
 2025-07-29 09:17:24 +00:00
Agate, Jesse 0541d73cbd amd/vpelib: Use Ceil Division Macro 
Use available ceil division macro

[WHY]
Code Cleanup

[HOW]
Use available macro

Reviewed-by: Roy Chan <Roy.Chan@amd.com>
Reviewed-by: Navid Assadian <Navid.Assadian@amd.com>
Acked-by: Chuanyu Tseng <Chuanyu.Tseng@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36433>
 2025-07-29 09:17:24 +00:00
Erico Nunes d620529ddb lima: ppir: fix check for discard_block in optimization 
uses_discard may be set when the nir shader contains a 'discard'
implemented with a nir 'terminate', in that case it may stil not
necessarily have a discard block.
Fixes a crash in shaders that have comp->uses_discard but no
comp->discard_block.

Fixes: fa9ddbe82b ("lima: ppir: optimize branches")

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36350>
 2025-07-29 08:55:02 +00:00
Yinjie Yao 740daef360 radeonsi/vcn: Enable preencode on VCN5.0 
two_pass_search_center_map_mode will need to be disabled on VCN5.0
due to hardware limitations.

Signed-off-by: Yinjie Yao <yinjie.yao@amd.com>
Reviewed-by: Boyuan Zhang <boyuan.zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36380>
 2025-07-29 08:26:08 +00:00
Yiwei Zhang 037fd5704a venus: set wsi alias binding memoryOffset to zero 
This aligns with common wsi and Android expectations and obeys the spec
for dedicated wsi mem alloc.

Reviewed-by: Antonio Ospite <antonio.ospite@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36388>
 2025-07-29 07:50:11 +00:00
Yiwei Zhang e559d76066 venus: drop is_wsi tracking and some asserts 
This is to help with kms support.

Reviewed-by: Antonio Ospite <antonio.ospite@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36388>
 2025-07-29 07:50:11 +00:00
Yiwei Zhang 8a156fb695 venus: drop cached ahb buffer memory types 
No longer needed as we relocated the type fix to mem alloc time even for
non-dedicated export alloc.

Reviewed-by: Antonio Ospite <antonio.ospite@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36388>
 2025-07-29 07:50:10 +00:00
Yiwei Zhang ca97816136 venus: rework AHB memory import 
We don't need the host dma-buf size anymore since the blob mapping size
has been made passive.

Reviewed-by: Antonio Ospite <antonio.ospite@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36388>
 2025-07-29 07:50:10 +00:00
Yiwei Zhang 87b1a46d88 venus: adopt vk_common_GetAndroidHardwareBufferPropertiesANDROID 
This is based on:
1. external format handling has been made passive
2. blob mapping size has been made passive
3. common helper has improved mem type reporting

Reviewed-by: Antonio Ospite <antonio.ospite@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36388>
 2025-07-29 07:50:09 +00:00
Yiwei Zhang aac51c3a0b vulkan/android: improve memoryTypeBits reporting in AHB props query 
Instead of reporting all memory types being compatible, at least we can
limit the types to those compatible for dma-buf import. Optionally, we
can do even better here to actually create the image or buffer with the
AHB to get more accurate memory type bits for memory import. However, it
is optional since we can touch up in the common layer upon actual AHB
import time.

Reviewed-by: Antonio Ospite <antonio.ospite@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36388>
 2025-07-29 07:50:09 +00:00
Job Noorman 04a182417e ir3/shared_ra: don't reuse src of different halfness 
Avoid reusing the src of an ALU/SFU instruction when its halfness is
different from the dst. A difference in halfness would introduce a (ss)
sync and unnecessarily increase ss-stall.

Totals from 8261 (5.02% of 164705) affected shaders:
Instrs: 10044160 -> 10044390 (+0.00%); split: -0.04%, +0.04%
CodeSize: 19875094 -> 19879238 (+0.02%); split: -0.08%, +0.10%
NOPs: 2249893 -> 2249273 (-0.03%); split: -0.14%, +0.11%
MOVs: 426644 -> 426565 (-0.02%); split: -0.24%, +0.23%
COVs: 134819 -> 134810 (-0.01%); split: -0.06%, +0.05%
(ss): 264012 -> 260680 (-1.26%); split: -1.34%, +0.08%
(sy): 122711 -> 122851 (+0.11%); split: -0.07%, +0.18%
(ss)-stall: 1111161 -> 1100625 (-0.95%); split: -1.07%, +0.12%
(sy)-stall: 3650422 -> 3651422 (+0.03%); split: -0.15%, +0.17%
STPs: 8693 -> 8701 (+0.09%); split: -0.08%, +0.17%
LDPs: 16814 -> 16815 (+0.01%); split: -0.10%, +0.11%
Preamble Instrs: 2346201 -> 2351217 (+0.21%); split: -0.25%, +0.46%
Last helper: 3417842 -> 3417889 (+0.00%); split: -0.07%, +0.08%
Cat0: 2486420 -> 2485758 (-0.03%); split: -0.13%, +0.10%
Cat1: 613403 -> 614417 (+0.17%); split: -0.21%, +0.37%
Cat2: 3742181 -> 3742109 (-0.00%); split: -0.00%, +0.00%
Cat6: 81897 -> 81906 (+0.01%); split: -0.03%, +0.04%
Cat7: 254014 -> 253955 (-0.02%); split: -0.11%, +0.09%

Note that the slight increase in Cat1 is mostly from lowered copies (to
swz) and seems to be RA bad luck.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36376>
 2025-07-29 07:23:15 +00:00
Georg Lehmann b12db991eb aco/gfx10: optimize subgroupRotate(x, 32) and subgroupShuffleXor(x, 32) 
We don't have v_permlane64_b32 yet, but we can still optimize it using
shared vgprs. Using the DPP16 row mask, we can even avoid writing exec.

With v0 input/output and v24/v25 as shared vgprs, this results in:
v_mov_b32_dpp v24, v0 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0xf
v_mov_b32_dpp v25, v0 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf
v_mov_b32_dpp v0, v24 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf
v_mov_b32_dpp v0, v25 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0xf

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36390>
 2025-07-29 06:33:20 +00:00
Georg Lehmann eb4df58a3d aco/isel: refactor shared vgpr usage 
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36390>
 2025-07-29 06:33:20 +00:00
Georg Lehmann 8a2aca8d6f aco/select_alu: avoid vector get_alu_src for instructions with scalar operands 
Foz-DB Navi21:
Totals from 1 (0.00% of 80237) affected shaders:
Instrs: 22 -> 21 (-4.55%)
CodeSize: 112 -> 108 (-3.57%)
Latency: 392 -> 386 (-1.53%)
InvThroughput: 25 -> 24 (-4.00%)
Copies: 4 -> 3 (-25.00%)
PreVGPRs: 8 -> 4 (-50.00%)
VALU: 10 -> 9 (-10.00%)

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35728>
 2025-07-29 06:07:15 +00:00
Georg Lehmann ad9c340d86 aco: insert VALU s_delay_alu for WMMA 
This should avoid some SIMD stalls.

I think this special case was added to try to handle this case:

First Instruction: WMMA
Second Instruction: WMMA instruction with same VGPR of previous WMMA instruction’s Matrix D as Matrix C
Stall if the first and second instruction are not the same type of WMMA or use ABS/NEG on SRC2 of the second instruction

If I read it correctly, we shouldn't need a delay if the type is the same and no
modifier is used. That's kind of complex to handle, so leave it for now.
Not inserting any delays likely hurts more than this.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36328>
 2025-07-29 05:48:29 +00:00
Georg Lehmann 413d0d2ec8 aco/statistics: update GFX12 WMMA cost 
Based on marketing numbers, but they seem to match RGP.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36328>
 2025-07-29 05:48:29 +00:00
Georg Lehmann 8f61c85880 aco/statistics: add latency to WMMA 
Assume the normal VALU latency of 4 cycles.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36328>
 2025-07-29 05:48:29 +00:00
Mike Blumenkrantz a30138c025 zink: verify that no generated tcs is ever in zink_context::gfx_stages 
this otherwise becomes very confusing to reason about

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36420>
 2025-07-28 20:10:00 +00:00
Mike Blumenkrantz 8af51a08fb zink: skip all glx piglit tests on anv-adl 
tried fixing this with weston changes to disable xwayland decor,
but that didn't work

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36422>
 2025-07-28 19:54:31 +00:00
Mel Henning a1b64fdc12 nak/mark_lcssa_invariants: Invalidate divergence 
Preserving this was resulting in validation errors like:
error: def->loop_invariant == BITSET_TEST(loop_invariance, def->index) (../src/compiler/nir/nir_validate.c:1890)

Fixes: 1d6082bf56 ("nouveau: switch to nir_metadata_divergence")
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36415>
 2025-07-28 19:37:51 +00:00
Juston Li e1ca09317e anv/android: refactor anb resolve to fix align assertion 
Retrieving memory requirement size and alignment via
anv_image_get_memory_requirements() return's 0 before surfaces are added
by resolve_anb_image() and will assert in align64() when align is 0:

Abort message: '../src/util/u_math.h:713: uint64_t align64(uint64_t, uint64_t): assertion "util_is_power_of_two_nonzero64(alignment)" failed'

Refactor out anv_image_bind_from_gralloc() into resolve_anb_image() so
the checks are performed after the surface is adds.

Resolving also requires API 29 so return VK_ERROR_EXTENSION_NOT_PRESENT
without it.

Fixes: 43cb986d9e ("anv/android: resolve ANB swapchain images on bind")
Signed-off-by: Juston Li <justonli@google.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36060>
 2025-07-28 18:54:08 +00:00
Marek Olšák 35e1000072 radeonsi/ci: update gfx12 and other failures 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36382>
 2025-07-28 18:36:14 +00:00
Marek Olšák ff42bf8b11 radeonsi/ci: don't build GLES CTS separately 
GLES tests are available in GL CTS too.

Delete the build_es directly manually.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36382>
 2025-07-28 18:36:14 +00:00
Marek Olšák 2294dcb25d radeonsi/ci: import piglit & cts build scripts 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36382>
 2025-07-28 18:36:14 +00:00
Mike Blumenkrantz 05cc38bb68 vulkan: silence typed_memcpy -Waddress warnings 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36413>
 2025-07-28 17:31:54 +00:00
Mike Blumenkrantz 0a536c7bf0 iris: silence perf_debug -Waddress warnings 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36413>
 2025-07-28 17:31:54 +00:00
Mike Blumenkrantz 1dae42308b crocus: silence perf_debug -Waddress warnings 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36413>
 2025-07-28 17:31:54 +00:00
Mike Blumenkrantz 7d2b36e50f zink: just check multiview availability to advertise extensions 
now that legacy renderpasses are dropped, this can be more general

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36417>
 2025-07-28 17:06:32 +00:00
Aksel Hjerpbakk c2284ae8a9 panvk: Use a single FBD for IR 
Introduce a scratch FBD that will be used in the event of IR. Also store
a subset of FBD words that are needed to construct the relevant IR FBD
in the scratch FBD memory.

This patch also increase the TILER_OOM_HANDLER_MAX_SIZE from 512 to 1024

Reviewed-by: Christoph Pillmayer <christoph.pillmayer@arm.com>
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34733>
 2025-07-28 16:08:20 +00:00
Aksel Hjerpbakk 8a35a98936 panvk: implement cs_extract64 & cs_extract_tuple 
Reviewed-by: Christoph Pillmayer <christoph.pillmayer@arm.com>
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34733>
 2025-07-28 16:08:20 +00:00
Aksel Hjerpbakk 5984ca8417 panvk: avoid cs jump block with no allocator 
Also initialize allocator to NULL for tiler OOM handler and assert
if capacity is sufficient in the event that allocator is NULL

Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34733>
 2025-07-28 16:08:20 +00:00
Jose Maria Casanova Crespo 20b61dcde2 v3d: Add V3D_TFU_READAHEAD padding for renderonly resources 
Fixes: 4e033ffb27 ("v3d: Add V3D_TFU_READAHEAD padding for allocated resources")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13508
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36407>
 2025-07-28 15:37:47 +00:00
Myrrh Periwinkle abcd02a07d gallium: Properly handle non-contiguous used sampler view indexes 
There is nothing guaranteeing that the currently used sampler view
indexes will be contiguous, which means the resulting extra sampler
views created by st_get_sampler_views may not be placed at the end of
the resulting array. Therefore, the exact indexes of these views must
be passed to the caller for releasing instead of simply assuming that
they will always be placed at the end.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13363
Fixes: 73da0dcddc ("gallium: eliminate frontend refcounting from samplerviews")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36397>
 2025-07-28 14:41:56 +00:00
Tomeu Vizoso 9fc2f71501 etnaviv/ml: Remove some skips that pass now 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34629>
 2025-07-28 14:14:33 +00:00
Tomeu Vizoso 3909d28924 etnaviv/ml: Support Transpose operation 
Similar to how we currently support Reshape, add a bypass
pseudo-operation and don't change the actual layout of the tensor.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34629>
 2025-07-28 14:14:33 +00:00
Tomeu Vizoso 0845acf578 teflon: Add support for Transpose 
Channel-first to channel-last, and the opposite.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34629>
 2025-07-28 14:14:33 +00:00
Tomeu Vizoso 3170b5f31c etnaviv/ml: Add support for Subtract 
Based on how we perform addition with a convolution, do something
similar for subtractions.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34629>
 2025-07-28 14:14:33 +00:00
Tomeu Vizoso 005ab1f0fe teflon: Add support for Subtract 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34629>
 2025-07-28 14:14:33 +00:00
Tomeu Vizoso a8a2ce1d74 etnaviv/ml: Add support for Logistic 
Add a TP job that makes use of a look up table to implement a piecewise
linear approximation of the logistic function.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34629>
 2025-07-28 14:14:32 +00:00
Tomeu Vizoso 9c6cab0458 teflon: Add support for Logistic 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34629>
 2025-07-28 14:14:31 +00:00
Tomeu Vizoso 67faa1525b etnaviv/ml: Add support for Absolute 
Add a TP job that makes use of a look up table to implement a piecewise
linear approximation of the absolute function.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34629>
 2025-07-28 14:14:31 +00:00
Tomeu Vizoso 519a8b0f4a teflon: Add support for Absolute 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34629>
 2025-07-28 14:14:31 +00:00
Tomeu Vizoso a1bb3f3c97 etnaviv/ml: Add support for non-fused ReLU 
Add a TP job that makes use of a look up table to implement a piecewise
linear approximation of the ReLU function.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34629>
 2025-07-28 14:14:30 +00:00