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Author SHA1 Message Date
Georg Lehmann
00a8be3414 nir: Print nir_selection_control_divergent_always_taken. 
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17921>
 2022-10-11 15:42:54 +00:00
Timur Kristóf
c0d0a7c176 nir: Add selection control enum for always taken divergent branches. 
The new enum is called nir_selection_control_divergent_always_taken,
and it's almost the same as nir_selection_control_flatten.
The main difference between the two is that "flatten" represents
a choice made by the application but "divergent_always_taken" may
be applied by the compiler stack when it thinks this is beneficial.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-By: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17921>
 2022-10-11 15:42:54 +00:00
Timur Kristóf
a2ec843727 nir: Document the flatten/dont_flatten selection control options. 
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-By: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17921>
 2022-10-11 15:42:53 +00:00
Sil Vilerino
ea6e69bb2b d3d12: Fix get_index7bits - Reuse previously freed indices 
Some apps do not always reuse resources contiguously and we need to search for a previous free index/slot

Reviewed-by: Giancarlo Devich <gdevich@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18944>
 2022-10-11 15:15:11 +00:00
Sil Vilerino
c8e8ce8359 d3d12: Add VP9 Decode support 
Reviewed-by: Giancarlo Devich <gdevich@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18944>
 2022-10-11 15:15:11 +00:00
Sil Vilerino
bb86bcad71 frontends/va: Add VP9 decode ref/mode_deltas information 
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18944>
 2022-10-11 15:15:11 +00:00
Sil Vilerino
baad2575ae frontends/va: Add VP9 decode multi slice information 
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18944>
 2022-10-11 15:15:11 +00:00
Ruijing Dong
4df54d97e8 frontends/va: fix av1 decoding image distortion issue 
problem:
when not using qmatrix, the qm_y, qm_u and qm_v value is set to 0,
which signals av1 decoder to use qmatix and causes confussion.

solution:
when not using qmatrix, set these values to 0xf.

fixed: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5632

Reviewed-by: Sil Vilerino <sivileri@microsoft.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19002>
 2022-10-11 14:59:49 +00:00
Rohan Garg
c0c243f1cb anv, iris: Disable pre fetching the binding table entries on DG2 
On DG2 the HW will fetch the binding entries into the cache
for every single thread when a compute walker is dispatched,
wiping out the advantages of the cache prefetch.

The spec also advises to not do a cache prefetch when we have more than
31 binding table entries, but most real world applications will never
hit that limit.

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18498>
 2022-10-11 15:16:09 +02:00
Samuel Pitoiset
d91c3bde8c radv: fix and rework shaders upload with GPL 
For fast-linking, we really want to upload the binaries directly in
a library to avoid creating and uploading at pipeline creation time.

To achieve that, add a radeon_winsys_bo pointer to radv_shader in
order to indicate that a shader is already uploaded. When a lib is
imported, the pipeline slab BO is also incremented to make sure it's
not freed when the lib is destroyed.

This also allows to free binaries right after they are uploaded.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Tatsuyuki Ishi <ishitatsuyuki@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18860>
 2022-10-11 10:06:53 +00:00
Mike Blumenkrantz
4b6b3f18f2 vk/graphics_state: don't set default sample locations if rast samples is dynamic 
dynamic rasterization samples got added late, and I forgot to update this

Fixes: 1deb83fb86 ("vulkan: Add more dynamic multisample states")

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18896>
 2022-10-11 06:58:19 +00:00
Timothy Arceri
ca0c429d32 radv: add radv_zero_vram workarounds for OpenGL games 
These are needed if the games are running on radv via zink.

Tested with "7 Days to Die"

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6449
Cc: mesa-stable

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19031>
 2022-10-11 06:36:59 +00:00
Kenneth Graunke
346994265a iris: Add miplevel parameters to iris_resource_texture_aux_usage 
Sometimes we only access a subset of a texture's miplevels, for example
when peforming GenerateMipmaps().  We want to be able to look for the
aux state being ISL_AUX_STATE_PASS_THROUGH for only the relevant
miplevels, rather than all of them, when deciding whether to bypass aux.

Avoids another occurrence of issues with reading via aux while in
passthrough state (see issue #6558), fixing misrendering in Chrome
and Electron apps while resizing the window to be smaller (#7272).

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7272
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com> [v1]
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19028>
 2022-10-11 04:46:17 +00:00
Tapani Pälli
21740580ce mesa: mark debug variables with ASSERTED 
To clean up compilation warnings about unused variables
when asserts are disabled.

v2: UNUSED -> ASSERTED (Eric Engestrom)

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19016>
 2022-10-11 04:14:30 +00:00
Tapani Pälli
b62d1c257e anv: mark debug variables with ASSERTED 
To clean up compilation warnings about unused variables
when asserts are disabled.

v2: UNUSED -> ASSERTED (Eric Engestrom)

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19016>
 2022-10-11 04:14:30 +00:00
Tapani Pälli
c9c9a5b78d intel/fs: mark debug variables with ASSERTED 
To clean up compilation warnings about unused variables
when asserts are disabled.

v2: UNUSED -> ASSERTED (Eric Engestrom)

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19016>
 2022-10-11 04:14:30 +00:00
Bas Nieuwenhuizen
30ce1676fe radv: Properly annotate all the invalid node usage. 
Reviewed-By: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18799>
 2022-10-10 23:35:25 +00:00
Bas Nieuwenhuizen
a8abdc0d89 radv: Add traversal backtracking with a short stack. 
So we can now work with arbitrarily deep BVHs.

Reviewed-By: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18799>
 2022-10-10 23:35:25 +00:00
Bas Nieuwenhuizen
251bba2fa0 radv: Split global & local bvh node variable. 
Need the local id later for follow up work.

Reviewed-By: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18799>
 2022-10-10 23:35:25 +00:00
Bas Nieuwenhuizen
e83e4fafc8 radv: Only emit parents from parents that actually end up in the tree. 
Otherwise the wrong parent link might be set.

This kinda relies on waves being launched in order which tends to
be the case on AMD. To avoid the busy-wait loop waiting on stuff
from the same subgroup we do the actual processing in the body of
the loop. This can have performance implications but mostly in the
case we'd otherwise deadlock, so meh.

Reviewed-By: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18799>
 2022-10-10 23:35:25 +00:00
Bas Nieuwenhuizen
4ce1b9b2ff radv: Generate parent links in BVH. 
Reviewed-By: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18799>
 2022-10-10 23:35:25 +00:00
Bas Nieuwenhuizen
1e2c95ac1f radv: Start the BVH after the header. 
First usage of the offset field, Can put more in it in the follow
up.

Reviewed-By: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18799>
 2022-10-10 23:35:25 +00:00
Bas Nieuwenhuizen
48ab1adda5 radv: Simplify buffer copy address generation. 
Reviewed-By: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18799>
 2022-10-10 23:35:25 +00:00
Bas Nieuwenhuizen
f1e1509c92 radv: Add a field for the offset of the bvh in the blas. 
So that we can put some metadata in front.

Reviewed-By: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18799>
 2022-10-10 23:35:25 +00:00
Bas Nieuwenhuizen
b0a385a6bd radv: Clean up unused fields in BVH IR. 
Reviewed-By: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18799>
 2022-10-10 23:35:25 +00:00
Connor Abbott
9b1087ca7c tu: Add compute shader instrlen workaround 
It's a bit unfortunate that this doesn't match any blob workaround that
we know of, but it seems to be necessary.

Closes: #5892
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19023>
 2022-10-10 21:04:18 +00:00
Connor Abbott
0dd60610dc freedreno: Add LABEL flush 
This seems like a debug thing, but the blob also seems to use it for
workarounds where an event is required but no actual work needs to be
done. For example CP_REG_WRITE uses it for various workarounds.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19023>
 2022-10-10 21:04:18 +00:00
Danylo Piliaiev
a1c372cd84 tu: Reset whether there is DS resolve for dynamic subpass 
Otherwise we use old invalid value.

Relevant CTS tests:
 dEQP-VK.pipeline.monolithic.multisample.misc.dynamic_rendering.multi_renderpass.r8g8b8a8_unorm_r16g16b16a16_sfloat_r16g16b16a16_*

Fixes: ed125e6cca
("tu: Initial support for dynamic rendering")

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18999>
 2022-10-10 20:45:51 +00:00
Jason Ekstrand
e4473c8f7a iris: Set SamplerCount in shader packets 
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18670>
 2022-10-10 20:23:01 +00:00
Karol Herbst
46143ffd63 iris: bump IRIS_MAX_GLOBAL_BINDINGS to 128 
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18670>
 2022-10-10 20:23:01 +00:00
Karol Herbst
f9c4dc3508 iris: speed up walking global bindings 
we can break on the first NULL resource as frontends always bind
contingous lists of resources without any gaps.

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18670>
 2022-10-10 20:23:01 +00:00
Karol Herbst
3ae84ea225 iris: use images_used instead of num_images 
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18670>
 2022-10-10 20:23:01 +00:00
Lionel Landwerlin
1e29a1a8c5 anv: add grl build dependency on entrypoints 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7446
Fixes: f3ddfd81b4 ("anv: Build BVHs on the GPU with GRL")
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19007>
 2022-10-10 19:14:07 +00:00
Danylo Piliaiev
4eba6d71a8 tu: Lazily init VSC to fix dynamic rendering in secondary cmdbufs 
Dynamic renderpasses need vsc_prim_strm_pitch, vsc_draw_strm_pitch
values, and a correct BO. The easiest way to solve this is to
lazily init VSC when it is needed, and not at every cmdbuf
initialization.

Fixes CTS tests (when running with TU_DEBUG=gmem,forcebin):
 dEQP-VK.draw.dynamic_rendering.complete_secondary_cmd_buff.*

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18996>
 2022-10-10 18:31:15 +00:00
Danylo Piliaiev
e70a2148e5 tu: Do not DCE unused output vars used for transform feedback 
Fixes CTS tests:
 dEQP-VK.transform_feedback.simple.multiquery_omit_write_1
 dEQP-VK.transform_feedback.simple.multiquery_omit_write_3

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19020>
 2022-10-10 18:12:04 +00:00
Rob Clark
f6098fb4f5 gallium/u_threaded: Add optional call-id tracing 
If enabled, use a scoped trace to see where calls happen on frontend vs
where they are pushed down to driver.  This is much lighter weight than
printf based tracing, but would still be an extra few instructions even
if perfetto tracing isn't active, so it is not enabled by default.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18927>
 2022-10-10 17:47:21 +00:00
Rob Clark
81925e2cc7 gallium/u_threaded: Add some atrace/perfetto 
Use the MESA_TRACE_BEGIN/END() macros which will generate perfetto
traces (if perfetto is enabled) otherwise atrace (if android build), in
either case creating track events which will show up on the frontend
thread in a perfetto trace, giving visibility into where syncs happen.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18927>
 2022-10-10 17:47:21 +00:00
Thomas Debesse
6d5921c623 nv50: call nir_lower_flrp 
Fix #7432: unknown nir_op flrp assertion

This copy-pastes src/gallium/drivers/radeonsi/si_shader_nir.c

The lower_flrp16 value differs given chipset >= NVISA_GV100_CHIPSET.

Signed-off-by: Thomas Debesse <dev@illwieckz.net>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19003>
 2022-10-10 17:22:49 +00:00
pal1000
ed2743eae5 clc/clover: Link clang statically when shared-llvm is disabled 
Makes things easier to handle when aiming for a static build

Cc: mesa-stable

Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18117>
 2022-10-10 12:20:30 +00:00
Erik Faye-Lund
55f6a2bb51 gallium: normalized_coords -> unnormalized_coords 
A lot of code zero-initializes pipe_sampler_state, and sets the states
the non-zero fields manually. This means that normalized_coords is the
"default" setting.

However, setting normalized_coords to true isn't allways allowed, and
we'd need to check PIPE_CAP_TEXRECT first. So it's not really the ideal
default here. There's recently been found quite a bit of bugs in this
area, where the state-tracker didn't properly lower texrects.

Let's switch this around to avoid more bugs like this in the future.

Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18971>
 2022-10-10 10:20:02 +00:00
Filip Gawin
4e7b9aaa06 r300: don't use smooth line if not requested 
Makes these tests passing:
dEQP-GLES2.functional.rasterization.interpolation.basic.line_loop_wide,UnexpectedPass
dEQP-GLES2.functional.rasterization.interpolation.basic.lines_wide,UnexpectedPass
dEQP-GLES2.functional.rasterization.interpolation.projected.line_loop_wide,UnexpectedPass
dEQP-GLES2.functional.rasterization.interpolation.projected.line_strip_wide,UnexpectedPass
dEQP-GLES2.functional.rasterization.interpolation.projected.lines_wide,UnexpectedPass
dEQP-GLES2.functional.rasterization.primitives.line_loop,UnexpectedPass
dEQP-GLES2.functional.rasterization.primitives.line_strip,UnexpectedPass
dEQP-GLES2.functional.rasterization.primitives.lines,UnexpectedPass
dEQP-GLES2.functional.rasterization.primitives.lines_wide,UnexpectedPass

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18979>
 2022-10-10 06:08:28 +00:00
Timothy Arceri
98944b327b util/radeonsi: enable zerovram workaround for Exanima 
The issue is very intermittent and can sometimes work fine
without the workaround but turning it on seems to resolve
any issues.

Issue: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6449

Cc: mesa-stable
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18935>
 2022-10-10 11:19:26 +11:00
Timothy Arceri
3200b5c46b util/conf: enable init to zero workaround for Exanima 
Fixes rendering issues on llvmpipe.

Issue: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6449

Cc: mesa-stable
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18935>
 2022-10-10 11:16:22 +11:00
Lionel Landwerlin
091b5b08d4 pps: enable track_event in intel.cfg 
Take the opportunity to prune some ftraces that are not that useful
and fill the buffer pretty fast.

Record time is bumped to 1.2s

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18930>
 2022-10-09 22:39:53 +03:00
Konstantin Seurer
e68adf19bc radv/rra: Transcode nodes recursively 
Instead of relying on a certain BVH layout, this patch traverses the BVH
from the root node which gets rid of any layout requirements.

Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18967>
 2022-10-09 17:39:31 +00:00
David Heidelberg
0c6c30d211 ci: uprev DXVK to 1.10.3 
Acked-by: Martin Roukala <martin.roukala@mupuf.org>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18888>
 2022-10-08 16:36:36 -05:00
Rob Clark
27aa172012 isaspec: Fix out of date comment 
Assembler support has existed for a long time.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18926>
 2022-10-08 14:25:29 +00:00
Rob Clark
c0cdc148f4 freedreno: Add perf-debug trace 
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18926>
 2022-10-08 14:25:29 +00:00
Rob Clark
f6f72b5629 freedreno/drm: Don't call kernel with no ops 
When called with FD_BO_PREP_FLUSH as the only op bit set, the intention
is to only sync with the submit-queue.. we shouldn't be calling down to
the kernel (where op==0 gets interpreted as MSM_PREP_READ).

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18926>
 2022-10-08 14:25:29 +00:00
Rob Clark
6dcc524035 freedreno: Use TC cpu-storage to shadow buffers 
We still use the shadow path for non-buffer updates, where TC isn't
playing any tricks.  But for correctness we need to use the cpu-
storage approach, instead of buffer shadowing, otherwise we can race
with the frontend thread for PIPE_MAP_UNSYNCHRONIZED access.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7262
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18926>
 2022-10-08 14:25:28 +00:00