brw: Allow additional flags registers on Xe2+

Xe2 adds two more flags registers. We barely use the second flags
register on previous platforms, so the omission was not previously
noticed.

There are several efforts in progress that will add using of more flags
registers.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35415>

src/intel/compiler/brw_analysis_performance.cpp

@@ -73,7 +73,7 @@ namespace {
       /* Flag register part of the ARF. */
       EU_DEPENDENCY_ID_FLAG0 = EU_DEPENDENCY_ID_ACCUM0 + 12,
       /* SBID token write completion.  Only used on Gfx12+. */
-      EU_DEPENDENCY_ID_SBID_WR0 = EU_DEPENDENCY_ID_FLAG0 + 8,
+      EU_DEPENDENCY_ID_SBID_WR0 = EU_DEPENDENCY_ID_FLAG0 + 16,
       /* SBID token read completion.  Only used on Gfx12+. */
       EU_DEPENDENCY_ID_SBID_RD0 = EU_DEPENDENCY_ID_SBID_WR0 + 32,
       /* Number of computation dependencies currently tracked. */

src/intel/compiler/brw_eu.h

@@ -73,8 +73,8 @@ struct brw_insn_state {
 
    bool pred_inv:1;
 
-   /* Flag subreg.  Bottom bit is subreg, top bit is reg */
-   unsigned flag_subreg:2;
+   /* Flag subreg.  Bottom bit is subreg, top bits are reg */
+   unsigned flag_subreg:3;
 
    bool acc_wr_control:1;
 };

src/intel/compiler/brw_schedule_instructions.cpp

@@ -1253,7 +1253,7 @@ brw_instruction_scheduler::calculate_deps()
     * After register allocation, reg_offsets are gone and we track individual
     * GRF registers.
     */
-   schedule_node *last_conditional_mod[8] = {};
+   schedule_node *last_conditional_mod[16] = {};
    schedule_node *last_accumulator_write = NULL;
    /* Fixed HW registers are assumed to be separate from the virtual
     * GRFs, so they can be tracked separately.  We don't really write