diff --git a/src/intel/compiler/brw_analysis_performance.cpp b/src/intel/compiler/brw_analysis_performance.cpp
index 5c11a63878c..d40d3aa3d61 100644
--- a/src/intel/compiler/brw_analysis_performance.cpp
+++ b/src/intel/compiler/brw_analysis_performance.cpp
@@ -73,7 +73,7 @@ namespace {
       /* Flag register part of the ARF. */
       EU_DEPENDENCY_ID_FLAG0 = EU_DEPENDENCY_ID_ACCUM0 + 12,
       /* SBID token write completion.  Only used on Gfx12+. */
-      EU_DEPENDENCY_ID_SBID_WR0 = EU_DEPENDENCY_ID_FLAG0 + 8,
+      EU_DEPENDENCY_ID_SBID_WR0 = EU_DEPENDENCY_ID_FLAG0 + 16,
       /* SBID token read completion.  Only used on Gfx12+. */
       EU_DEPENDENCY_ID_SBID_RD0 = EU_DEPENDENCY_ID_SBID_WR0 + 32,
       /* Number of computation dependencies currently tracked. */
diff --git a/src/intel/compiler/brw_eu.h b/src/intel/compiler/brw_eu.h
index c54e68efeaa..0bb8ec67d5e 100644
--- a/src/intel/compiler/brw_eu.h
+++ b/src/intel/compiler/brw_eu.h
@@ -73,8 +73,8 @@ struct brw_insn_state {
 
    bool pred_inv:1;
 
-   /* Flag subreg.  Bottom bit is subreg, top bit is reg */
-   unsigned flag_subreg:2;
+   /* Flag subreg.  Bottom bit is subreg, top bits are reg */
+   unsigned flag_subreg:3;
 
    bool acc_wr_control:1;
 };
diff --git a/src/intel/compiler/brw_schedule_instructions.cpp b/src/intel/compiler/brw_schedule_instructions.cpp
index 888f529ad93..54523dde13c 100644
--- a/src/intel/compiler/brw_schedule_instructions.cpp
+++ b/src/intel/compiler/brw_schedule_instructions.cpp
@@ -1253,7 +1253,7 @@ brw_instruction_scheduler::calculate_deps()
     * After register allocation, reg_offsets are gone and we track individual
     * GRF registers.
     */
-   schedule_node *last_conditional_mod[8] = {};
+   schedule_node *last_conditional_mod[16] = {};
    schedule_node *last_accumulator_write = NULL;
    /* Fixed HW registers are assumed to be separate from the virtual
     * GRFs, so they can be tracked separately.  We don't really write