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radv: remove useless gfx10_ngg_info::enable_vertex_grouping

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It's always TRUE and this will simplify future changes.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18776>
This commit is contained in:
Samuel Pitoiset
2022-09-19 18:43:16 +02:00
parent efd83e9627
commit e053f6feb3
4 changed files with 4 additions and 12 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/amd/vulkan/radv_pipeline.c
+2 -6
View File
@@ -5013,16 +5013,12 @@ radv_pipeline_emit_hw_ngg(struct radeon_cmdbuf *ctx_cs, struct radeon_cmdbuf *cs
if (pdevice->rad_info.gfx_level >= GFX11) {
ge_cntl = S_03096C_PRIMS_PER_SUBGRP(ngg_state->max_gsprims) |
S_03096C_VERTS_PER_SUBGRP(ngg_state->enable_vertex_grouping
? ngg_state->hw_max_esverts
: 256) | /* 256 = disable vertex grouping */
S_03096C_VERTS_PER_SUBGRP(ngg_state->hw_max_esverts) |
S_03096C_BREAK_PRIMGRP_AT_EOI(break_wave_at_eoi) |
S_03096C_PRIM_GRP_SIZE_GFX11(256);
} else {
ge_cntl = S_03096C_PRIM_GRP_SIZE_GFX10(ngg_state->max_gsprims) |
S_03096C_VERT_GRP_SIZE(ngg_state->enable_vertex_grouping
? ngg_state->hw_max_esverts
: 256) | /* 256 = disable vertex grouping */
S_03096C_VERT_GRP_SIZE(ngg_state->hw_max_esverts) |
S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi);
}
src/amd/vulkan/radv_shader.c
+1 -1
View File
@@ -1368,7 +1368,7 @@ void radv_lower_ngg(struct radv_device *device, struct radv_pipeline_stage *ngg_
}
/* Invocations that process an input vertex */
unsigned max_vtx_in = MIN2(256, ngg_info->enable_vertex_grouping ? ngg_info->hw_max_esverts : num_vertices_per_prim * ngg_info->max_gsprims);
unsigned max_vtx_in = MIN2(256, ngg_info->hw_max_esverts);
if (nir->info.stage == MESA_SHADER_VERTEX ||
nir->info.stage == MESA_SHADER_TESS_EVAL) {
src/amd/vulkan/radv_shader.h
-1
View File
@@ -228,7 +228,6 @@ struct gfx10_ngg_info {
uint32_t vgt_esgs_ring_itemsize;
uint32_t esgs_ring_size;
bool max_vert_out_per_gs_instance;
bool enable_vertex_grouping;
};
struct radv_shader_info {
src/amd/vulkan/radv_shader_info.c
+1 -4
View File
@@ -500,7 +500,6 @@ gather_shader_info_mesh(const nir_shader *nir, struct radv_shader_info *info)
* - with GS_FAST_LAUNCH=1 every lane's VGPRs are initialized to the same input vertex index
*
*/
ngg_info->enable_vertex_grouping = true;
ngg_info->esgs_ring_size = 1;
ngg_info->hw_max_esverts = 1;
ngg_info->max_gsprims = 1;
@@ -1177,7 +1176,6 @@ gfx10_get_ngg_info(const struct radv_device *device, struct radv_pipeline_stage
out->prim_amp_factor = prim_amp_factor;
out->max_vert_out_per_gs_instance = max_vert_out_per_gs_instance;
out->ngg_emit_size = max_gsprims * gsprim_lds_size;
out->enable_vertex_grouping = true;
/* Don't count unusable vertices. */
out->esgs_ring_size = MIN2(max_esverts, max_gsprims * max_verts_per_prim) * esvert_lds_size * 4;
@@ -1226,8 +1224,7 @@ radv_determine_ngg_settings(struct radv_device *device, struct radv_pipeline_sta
/* Invocations that process an input vertex */
const struct gfx10_ngg_info *ngg_info = &es_stage->info.ngg_info;
unsigned max_vtx_in = MIN2(256, ngg_info->enable_vertex_grouping ?
ngg_info->hw_max_esverts : num_vertices_per_prim * ngg_info->max_gsprims);
unsigned max_vtx_in = MIN2(256, ngg_info->hw_max_esverts);
unsigned lds_bytes_if_culling_off = 0;
/* We need LDS space when VS needs to export the primitive ID. */