diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 1ef00dbe705..76d1ec0e51c 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -5013,16 +5013,12 @@ radv_pipeline_emit_hw_ngg(struct radeon_cmdbuf *ctx_cs, struct radeon_cmdbuf *cs
 
    if (pdevice->rad_info.gfx_level >= GFX11) {
       ge_cntl = S_03096C_PRIMS_PER_SUBGRP(ngg_state->max_gsprims) |
-                S_03096C_VERTS_PER_SUBGRP(ngg_state->enable_vertex_grouping
-                                          ? ngg_state->hw_max_esverts
-                                          : 256) | /* 256 = disable vertex grouping */
+                S_03096C_VERTS_PER_SUBGRP(ngg_state->hw_max_esverts) |
                 S_03096C_BREAK_PRIMGRP_AT_EOI(break_wave_at_eoi) |
                 S_03096C_PRIM_GRP_SIZE_GFX11(256);
    } else {
       ge_cntl = S_03096C_PRIM_GRP_SIZE_GFX10(ngg_state->max_gsprims) |
-                S_03096C_VERT_GRP_SIZE(ngg_state->enable_vertex_grouping
-                                          ? ngg_state->hw_max_esverts
-                                          : 256) | /* 256 = disable vertex grouping */
+                S_03096C_VERT_GRP_SIZE(ngg_state->hw_max_esverts) |
                 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi);
    }
 
diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index 52d2e7c24f0..7824480fbc4 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -1368,7 +1368,7 @@ void radv_lower_ngg(struct radv_device *device, struct radv_pipeline_stage *ngg_
    }
 
    /* Invocations that process an input vertex */
-   unsigned max_vtx_in = MIN2(256, ngg_info->enable_vertex_grouping ? ngg_info->hw_max_esverts : num_vertices_per_prim * ngg_info->max_gsprims);
+   unsigned max_vtx_in = MIN2(256, ngg_info->hw_max_esverts);
 
    if (nir->info.stage == MESA_SHADER_VERTEX ||
        nir->info.stage == MESA_SHADER_TESS_EVAL) {
diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h
index c5dadd2c628..f6c9f413bf1 100644
--- a/src/amd/vulkan/radv_shader.h
+++ b/src/amd/vulkan/radv_shader.h
@@ -228,7 +228,6 @@ struct gfx10_ngg_info {
    uint32_t vgt_esgs_ring_itemsize;
    uint32_t esgs_ring_size;
    bool max_vert_out_per_gs_instance;
-   bool enable_vertex_grouping;
 };
 
 struct radv_shader_info {
diff --git a/src/amd/vulkan/radv_shader_info.c b/src/amd/vulkan/radv_shader_info.c
index 8d31675b309..3ddcdaab39c 100644
--- a/src/amd/vulkan/radv_shader_info.c
+++ b/src/amd/vulkan/radv_shader_info.c
@@ -500,7 +500,6 @@ gather_shader_info_mesh(const nir_shader *nir, struct radv_shader_info *info)
     * - with GS_FAST_LAUNCH=1 every lane's VGPRs are initialized to the same input vertex index
     *
     */
-   ngg_info->enable_vertex_grouping = true;
    ngg_info->esgs_ring_size = 1;
    ngg_info->hw_max_esverts = 1;
    ngg_info->max_gsprims = 1;
@@ -1177,7 +1176,6 @@ gfx10_get_ngg_info(const struct radv_device *device, struct radv_pipeline_stage
    out->prim_amp_factor = prim_amp_factor;
    out->max_vert_out_per_gs_instance = max_vert_out_per_gs_instance;
    out->ngg_emit_size = max_gsprims * gsprim_lds_size;
-   out->enable_vertex_grouping = true;
 
    /* Don't count unusable vertices. */
    out->esgs_ring_size = MIN2(max_esverts, max_gsprims * max_verts_per_prim) * esvert_lds_size * 4;
@@ -1226,8 +1224,7 @@ radv_determine_ngg_settings(struct radv_device *device, struct radv_pipeline_sta
 
    /* Invocations that process an input vertex */
    const struct gfx10_ngg_info *ngg_info = &es_stage->info.ngg_info;
-   unsigned max_vtx_in = MIN2(256, ngg_info->enable_vertex_grouping ?
-         ngg_info->hw_max_esverts : num_vertices_per_prim * ngg_info->max_gsprims);
+   unsigned max_vtx_in = MIN2(256, ngg_info->hw_max_esverts);
 
    unsigned lds_bytes_if_culling_off = 0;
    /* We need LDS space when VS needs to export the primitive ID. */