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aco/gfx12: increase maximum global/scratch offset

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fossil-db (gfx1201):
Totals from 29 (0.04% of 79377) affected shaders:
Instrs: 1439082 -> 1439070 (-0.00%)
CodeSize: 7641688 -> 7641608 (-0.00%)
Latency: 9836296 -> 9836280 (-0.00%)
VALU: 799504 -> 799496 (-0.00%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34730>
This commit is contained in:
Rhys Perry
2025-04-23 17:06:31 +01:00
committed by Marge Bot
parent 02d193f058
commit d987d5e341
3 changed files with 12 additions and 10 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/amd/compiler/aco_ir.cpp
+4 -1
View File
@@ -168,7 +168,10 @@ init_program(Program* program, Stage stage, const struct aco_shader_info* info,
program->family == CHIP_MI100 || program->family == CHIP_MI200)
program->dev.fused_mad_mix = true;
if (program->gfx_level >= GFX11) {
if (program->gfx_level >= GFX12) {
program->dev.scratch_global_offset_min = -8388608;
program->dev.scratch_global_offset_max = 8388607;
} else if (program->gfx_level >= GFX11) {
program->dev.scratch_global_offset_min = -4096;
program->dev.scratch_global_offset_max = 4095;
} else if (program->gfx_level >= GFX10 || program->gfx_level == GFX8) {
src/amd/compiler/aco_ir.h
+7 -8
View File
@@ -1699,12 +1699,11 @@ static_assert(sizeof(MIMG_instruction) == sizeof(Instruction) + 8, "Unexpected p
struct FLAT_instruction : public Instruction {
memory_sync_info sync;
ac_hw_cache_flags cache;
bool lds : 1;
bool nv : 1;
bool disable_wqm : 1; /* Require an exec mask without helper invocations */
uint8_t padding0 : 5;
uint8_t padding1;
int16_t offset; /* Vega/Navi only */
int32_t offset : 24;
uint32_t lds : 1;
uint32_t nv : 1;
uint32_t disable_wqm : 1; /* Require an exec mask without helper invocations */
uint32_t padding0 : 5;
};
static_assert(sizeof(FLAT_instruction) == sizeof(Instruction) + 8, "Unexpected padding");
@@ -2102,8 +2101,8 @@ struct DeviceInfo {
bool xnack_enabled = false;
bool sram_ecc_enabled = false;
int16_t scratch_global_offset_min;
int16_t scratch_global_offset_max;
int32_t scratch_global_offset_min;
int32_t scratch_global_offset_max;
unsigned max_nsa_vgprs;
/* Note that GFX6/7 ignore the low 2 bits and this is only for positive offsets. */
src/amd/compiler/aco_opcodes.py
+1 -1
View File
@@ -184,7 +184,7 @@ class Format(IntEnum):
return [('uint8_t', 'opsel', 0),
('unsigned', 'wait_exp', 7)]
elif self in [Format.FLAT, Format.GLOBAL, Format.SCRATCH]:
return [('int16_t', 'offset', 0),
return [('int32_t', 'offset', 0),
('memory_sync_info', 'sync', 'memory_sync_info()'),
('ac_hw_cache_flags', 'cache', '{{0, 0, 0, 0, 0}}'),
('bool', 'lds', 'false'),