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anv: reduce cache flushing for indirect commands on Gfx12.5+

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Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27257>
This commit is contained in:
Lionel Landwerlin
2024-01-25 10:52:23 +02:00
committed by Marge Bot
parent 36f23bf96d
commit d699600da1
1 changed files with 8 additions and 3 deletions
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src/intel/vulkan/genX_cmd_buffer.c
+8 -3
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@@ -3103,11 +3103,16 @@ anv_pipe_invalidate_bits_for_access_flags(struct anv_cmd_buffer *cmd_buffer,
* UBO from the buffer, so we need to invalidate constant cache.
*/
pipe_bits |= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT;
pipe_bits |= ANV_PIPE_DATA_CACHE_FLUSH_BIT;
/* Tile cache flush needed For CmdDipatchIndirect since command
* streamer and vertex fetch aren't L3 coherent.
/* Indirect commands are sometimes implemented with the command
* streamer. On Gfx12.5+ we know experimentally that the command
* streamer is coherent with L3. Because that's not the case on
* previous generations we need to flush the data & tile caches.
*/
#if GFX_VERx10 < 125
pipe_bits |= ANV_PIPE_DATA_CACHE_FLUSH_BIT;
pipe_bits |= ANV_PIPE_TILE_CACHE_FLUSH_BIT;
#endif
break;
case VK_ACCESS_2_INDEX_READ_BIT:
case VK_ACCESS_2_VERTEX_ATTRIBUTE_READ_BIT: