From d699600da1db483b142d71e777b3ed1bc6576a4a Mon Sep 17 00:00:00 2001 From: Lionel Landwerlin Date: Thu, 25 Jan 2024 10:52:23 +0200 Subject: [PATCH] anv: reduce cache flushing for indirect commands on Gfx12.5+ MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Lionel Landwerlin Reviewed-by: José Roberto de Souza Part-of: --- src/intel/vulkan/genX_cmd_buffer.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c index ad833b4ec1b..90b8d0bdda5 100644 --- a/src/intel/vulkan/genX_cmd_buffer.c +++ b/src/intel/vulkan/genX_cmd_buffer.c @@ -3103,11 +3103,16 @@ anv_pipe_invalidate_bits_for_access_flags(struct anv_cmd_buffer *cmd_buffer, * UBO from the buffer, so we need to invalidate constant cache. */ pipe_bits |= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT; - pipe_bits |= ANV_PIPE_DATA_CACHE_FLUSH_BIT; - /* Tile cache flush needed For CmdDipatchIndirect since command - * streamer and vertex fetch aren't L3 coherent. + + /* Indirect commands are sometimes implemented with the command + * streamer. On Gfx12.5+ we know experimentally that the command + * streamer is coherent with L3. Because that's not the case on + * previous generations we need to flush the data & tile caches. */ +#if GFX_VERx10 < 125 + pipe_bits |= ANV_PIPE_DATA_CACHE_FLUSH_BIT; pipe_bits |= ANV_PIPE_TILE_CACHE_FLUSH_BIT; +#endif break; case VK_ACCESS_2_INDEX_READ_BIT: case VK_ACCESS_2_VERTEX_ATTRIBUTE_READ_BIT: