radv/amdgpu: simplify cs_execute_ib()
It's only used for executing IB2 on GFX. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30809>
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@@ -805,30 +805,12 @@ radv_amdgpu_cs_execute_ib(struct radeon_cmdbuf *_cs, struct radeon_winsys_bo *bo
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return;
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assert(ib_va && ib_va % cs->ws->info.ip[cs->hw_ip].ib_alignment == 0);
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assert(cs->hw_ip == AMD_IP_GFX && cdw <= ~C_3F2_IB_SIZE);
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if (cs->hw_ip == AMD_IP_GFX && cs->use_ib) {
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assert(cdw <= ~C_3F2_IB_SIZE);
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radeon_emit(&cs->base, PKT3(PKT3_INDIRECT_BUFFER, 2, predicate));
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radeon_emit(&cs->base, ib_va);
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radeon_emit(&cs->base, ib_va >> 32);
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radeon_emit(&cs->base, cdw);
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} else {
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const uint32_t ib_size = radv_amdgpu_cs_get_initial_size(cs->ws, cs->hw_ip);
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VkResult result;
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/* Finalize the current CS without chaining to execute the external IB. */
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radv_amdgpu_cs_finalize(_cs);
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radv_amdgpu_cs_add_ib_buffer(cs, bo, ib_va, cdw);
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/* Start a new CS which isn't chained to any previous CS. */
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result = radv_amdgpu_cs_get_new_ib(_cs, ib_size);
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if (result != VK_SUCCESS) {
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cs->base.cdw = 0;
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cs->status = result;
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}
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}
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radeon_emit(&cs->base, PKT3(PKT3_INDIRECT_BUFFER, 2, predicate));
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radeon_emit(&cs->base, ib_va);
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radeon_emit(&cs->base, ib_va >> 32);
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radeon_emit(&cs->base, cdw);
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}
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static void
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