i965: Move the CC VP to state streaming.

This is in a way a revert of f5bb775fd1.
The tiny win that had will be overwhelmed by the win of using the gen6
dynamic state base address.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

src/mesa/drivers/dri/i965/Makefile

@@ -61,7 +61,6 @@ DRIVER_SOURCES = \
 	brw_sf.c \
 	brw_sf_emit.c \
 	brw_sf_state.c \
-	brw_state.c \
 	brw_state_batch.c \
 	brw_state_cache.c \
 	brw_state_dump.c \

src/mesa/drivers/dri/i965/brw_cc.c

@@ -37,28 +37,36 @@
 #include "main/macros.h"
 #include "intel_batchbuffer.h"
 
-void
-brw_update_cc_vp(struct brw_context *brw)
+static void
+prepare_cc_vp(struct brw_context *brw)
 {
    struct gl_context *ctx = &brw->intel.ctx;
-   struct brw_cc_viewport ccv;
+   struct brw_cc_viewport *ccv;
 
-   memset(&ccv, 0, sizeof(ccv));
+   ccv = brw_state_batch(brw, sizeof(*ccv), 32, &brw->cc.vp_offset);
 
    /* _NEW_TRANSOFORM */
    if (ctx->Transform.DepthClamp) {
       /* _NEW_VIEWPORT */
-      ccv.min_depth = MIN2(ctx->Viewport.Near, ctx->Viewport.Far);
-      ccv.max_depth = MAX2(ctx->Viewport.Near, ctx->Viewport.Far);
+      ccv->min_depth = MIN2(ctx->Viewport.Near, ctx->Viewport.Far);
+      ccv->max_depth = MAX2(ctx->Viewport.Near, ctx->Viewport.Far);
    } else {
-      ccv.min_depth = 0.0;
-      ccv.max_depth = 1.0;
+      ccv->min_depth = 0.0;
+      ccv->max_depth = 1.0;
    }
 
-   drm_intel_bo_unreference(brw->cc.vp_bo);
-   brw->cc.vp_bo = brw_cache_data(&brw->cache, BRW_CC_VP, &ccv, sizeof(ccv));
+   brw->state.dirty.cache |= CACHE_NEW_CC_VP;
 }
 
+const struct brw_tracked_state brw_cc_vp = {
+   .dirty = {
+      .mesa = _NEW_VIEWPORT | _NEW_TRANSFORM,
+      .brw = BRW_NEW_BATCH,
+      .cache = 0
+   },
+   .prepare = prepare_cc_vp
+};
+
 /**
  * Modify blend function to force destination alpha to 1.0
  *
@@ -81,11 +89,6 @@ fix_xRGB_alpha(GLenum function)
    return function;
 }
 
-static void prepare_cc_unit(struct brw_context *brw)
-{
-   brw_add_validated_bo(brw, brw->cc.vp_bo);
-}
-
 /**
  * Creates the state cache entry for the given CC unit key.
  */
@@ -209,7 +212,8 @@ static void upload_cc_unit(struct brw_context *brw)
       cc->cc5.statistics_enable = 1;
 
    /* CACHE_NEW_CC_VP */
-   cc->cc4.cc_viewport_state_offset = brw->cc.vp_bo->offset >> 5; /* reloc */
+   cc->cc4.cc_viewport_state_offset = (intel->batch.bo->offset +
+				       brw->cc.vp_offset) >> 5; /* reloc */
 
    brw->state.dirty.cache |= CACHE_NEW_CC_UNIT;
 
@@ -217,7 +221,7 @@ static void upload_cc_unit(struct brw_context *brw)
    drm_intel_bo_emit_reloc(brw->intel.batch.bo,
 			   (brw->cc.state_offset +
 			    offsetof(struct brw_cc_unit_state, cc4)),
-			   brw->cc.vp_bo, 0,
+			   intel->batch.bo, brw->cc.vp_offset,
 			   I915_GEM_DOMAIN_INSTRUCTION, 0);
 }
 
@@ -227,7 +231,6 @@ const struct brw_tracked_state brw_cc_unit = {
       .brw = BRW_NEW_BATCH,
       .cache = CACHE_NEW_CC_VP
    },
-   .prepare = prepare_cc_unit,
    .emit = upload_cc_unit,
 };
 

src/mesa/drivers/dri/i965/brw_context.c

@@ -51,9 +51,6 @@ static void brwInitDriverFunctions( struct dd_function_table *functions )
 
    brwInitFragProgFuncs( functions );
    brw_init_queryobj_functions(functions);
-
-   functions->Enable = brw_enable;
-   functions->DepthRange = brw_depth_range;
 }
 
 GLboolean brwCreateContext( int api,
@@ -232,11 +229,6 @@ GLboolean brwCreateContext( int api,
 
    brw_draw_init( brw );
 
-   /* Now that most driver functions are hooked up, initialize some of the
-    * immediate state.
-    */
-   brw_update_cc_vp(brw);
-
    return GL_TRUE;
 }
 

src/mesa/drivers/dri/i965/brw_context.h

@@ -715,7 +715,6 @@ struct brw_context
    struct {
       /* gen4 */
       drm_intel_bo *prog_bo;
-      drm_intel_bo *vp_bo;
 
       /* gen6 */
       drm_intel_bo *blend_state_bo;
@@ -723,6 +722,7 @@ struct brw_context
       drm_intel_bo *color_calc_state_bo;
 
       uint32_t state_offset;
+      uint32_t vp_offset;
    } cc;
 
    struct {
@@ -792,9 +792,6 @@ void brwInitFragProgFuncs( struct dd_function_table *functions );
  */
 void brw_upload_urb_fence(struct brw_context *brw);
 
-/* brw_cc.c */
-void brw_update_cc_vp(struct brw_context *brw);
-
 /* brw_curbe.c
  */
 void brw_upload_cs_urb_state(struct brw_context *brw);
@@ -802,10 +799,6 @@ void brw_upload_cs_urb_state(struct brw_context *brw);
 /* brw_disasm.c */
 int brw_disasm (FILE *file, struct brw_instruction *inst, int gen);
 
-/* brw_state.c */
-void brw_enable(struct gl_context * ctx, GLenum cap, GLboolean state);
-void brw_depth_range(struct gl_context *ctx, GLclampd nearval, GLclampd farval);
-
 /*======================================================================
  * Inline conversion functions.  These are better-typed than the
  * macros used previously:

src/mesa/drivers/dri/i965/brw_state.c

@@ -1,49 +0,0 @@
-/*
- * Copyright © 2010 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- *
- * Authors:
- *    Eric Anholt <eric@anholt.net>
- *
- */
-
-#include "brw_context.h"
-
-void
-brw_enable(struct gl_context *ctx, GLenum cap, GLboolean state)
-{
-   struct brw_context *brw = brw_context(ctx);
-
-   switch (cap) {
-   case GL_DEPTH_CLAMP:
-      brw_update_cc_vp(brw);
-      break;
-   }
-}
-
-void
-brw_depth_range(struct gl_context *ctx, GLclampd nearval, GLclampd farval)
-{
-   struct brw_context *brw = brw_context(ctx);
-
-   if (ctx->Transform.DepthClamp)
-      brw_update_cc_vp(brw);
-}

src/mesa/drivers/dri/i965/brw_state.h

@@ -47,6 +47,7 @@ brw_add_validated_bo(struct brw_context *brw, drm_intel_bo *bo)
 };
 
 extern const struct brw_tracked_state brw_blend_constant_color;
+extern const struct brw_tracked_state brw_cc_vp;
 extern const struct brw_tracked_state brw_cc_unit;
 extern const struct brw_tracked_state brw_check_fallback;
 extern const struct brw_tracked_state brw_clip_prog;

src/mesa/drivers/dri/i965/brw_state_dump.c

@@ -250,21 +250,19 @@ static void dump_clip_viewport_state(struct brw_context *brw)
 
 static void dump_cc_viewport_state(struct brw_context *brw)
 {
+   struct intel_context *intel = &brw->intel;
    const char *name = "CC VP";
    struct brw_cc_viewport *vp;
    uint32_t vp_off;
 
-   if (brw->cc.vp_bo == NULL)
-      return;
+   drm_intel_bo_map(intel->batch.bo, GL_FALSE);
 
-   drm_intel_bo_map(brw->cc.vp_bo, GL_FALSE);
-
-   vp = brw->cc.vp_bo->virtual;
-   vp_off = brw->cc.vp_bo->offset;
+   vp = intel->batch.bo->virtual + brw->cc.vp_offset;
+   vp_off = intel->batch.bo->offset + brw->cc.vp_offset;
 
    state_out(name, vp, vp_off, 0, "min_depth = %f\n", vp->min_depth);
    state_out(name, vp, vp_off, 1, "max_depth = %f\n", vp->max_depth);
-   drm_intel_bo_unmap(brw->cc.vp_bo);
+   drm_intel_bo_unmap(intel->batch.bo);
 }
 
 static void dump_depth_stencil_state(struct brw_context *brw)

src/mesa/drivers/dri/i965/brw_state_upload.c

@@ -60,6 +60,7 @@ static const struct brw_tracked_state *gen4_atoms[] =
    &brw_curbe_offsets,
    &brw_recalculate_urb_fence,
 
+   &brw_cc_vp,
    &brw_cc_unit,
 
    &brw_vs_constants, /* Before vs_surfaces and constant_buffer */
@@ -119,6 +120,7 @@ static const struct brw_tracked_state *gen6_atoms[] =
    /* Command packets: */
    &brw_invarient_state,
 
+   &brw_cc_vp,
    &gen6_viewport_state,	/* must do after *_vp stages */
 
    &gen6_urb,

src/mesa/drivers/dri/i965/brw_vtbl.c

@@ -92,7 +92,6 @@ static void brw_destroy_context( struct intel_context *intel )
    dri_bo_release(&brw->wm.state_bo);
    dri_bo_release(&brw->wm.const_bo);
    dri_bo_release(&brw->cc.prog_bo);
-   dri_bo_release(&brw->cc.vp_bo);
    dri_bo_release(&brw->cc.blend_state_bo);
    dri_bo_release(&brw->cc.depth_stencil_state_bo);
    dri_bo_release(&brw->cc.color_calc_state_bo);

src/mesa/drivers/dri/i965/gen6_viewport_state.c

@@ -104,11 +104,6 @@ const struct brw_tracked_state gen6_sf_vp = {
    .prepare = prepare_sf_vp,
 };
 
-static void prepare_viewport_state_pointers(struct brw_context *brw)
-{
-   brw_add_validated_bo(brw, brw->cc.vp_bo);
-}
-
 static void upload_viewport_state_pointers(struct brw_context *brw)
 {
    struct intel_context *intel = &brw->intel;
@@ -122,7 +117,8 @@ static void upload_viewport_state_pointers(struct brw_context *brw)
 	     brw->clip.vp_offset);
    OUT_RELOC(intel->batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
 	     brw->sf.vp_offset);
-   OUT_RELOC(brw->cc.vp_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
+   OUT_RELOC(intel->batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
+	     brw->cc.vp_offset);
    ADVANCE_BATCH();
 }
 
@@ -134,6 +130,5 @@ const struct brw_tracked_state gen6_viewport_state = {
 		CACHE_NEW_SF_VP |
 		CACHE_NEW_CC_VP)
    },
-   .prepare = prepare_viewport_state_pointers,
    .emit = upload_viewport_state_pointers,
 };