radv: flush DFSM on CB_TARGET_MASK changes when it's emitted
To avoid performing the same check twice and to emit it at the right place. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20299>
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cb0a17652d
@@ -2425,8 +2425,16 @@ radv_emit_logic_op(struct radv_cmd_buffer *cmd_buffer)
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static void
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radv_emit_color_write(struct radv_cmd_buffer *cmd_buffer)
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{
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const struct radv_device *device = cmd_buffer->device;
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const struct radv_binning_settings *settings = &device->physical_device->binning_settings;
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const struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
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if (device->pbb_allowed && settings->context_states_per_bin > 1) {
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/* Flush DFSM on CB_TARGET_MASK changes. */
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radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
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radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
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}
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radeon_set_context_reg(cmd_buffer->cs, R_028238_CB_TARGET_MASK,
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d->color_write_mask & d->color_write_enable);
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}
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@@ -8491,18 +8499,6 @@ radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer, const struct r
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}
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}
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if (device->pbb_allowed) {
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struct radv_binning_settings *settings = &device->physical_device->binning_settings;
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if ((cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_COLOR_WRITE_ENABLE |
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RADV_CMD_DIRTY_DYNAMIC_COLOR_WRITE_MASK)) &&
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settings->context_states_per_bin > 1) {
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/* Break the batch on CB_TARGET_MASK changes. */
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radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
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radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
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}
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}
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/* Pre-compute some tessellation info that depend on the number of patch control points when the
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* bound pipeline declared this state as dynamic.
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*/
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