From cb0a17652d52730734f910bd059681f05848d47d Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Mon, 12 Dec 2022 16:37:21 +0100 Subject: [PATCH] radv: flush DFSM on CB_TARGET_MASK changes when it's emitted To avoid performing the same check twice and to emit it at the right place. Signed-off-by: Samuel Pitoiset Part-of: --- src/amd/vulkan/radv_cmd_buffer.c | 20 ++++++++------------ 1 file changed, 8 insertions(+), 12 deletions(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index b59fb0b8e6c..359ada47327 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -2425,8 +2425,16 @@ radv_emit_logic_op(struct radv_cmd_buffer *cmd_buffer) static void radv_emit_color_write(struct radv_cmd_buffer *cmd_buffer) { + const struct radv_device *device = cmd_buffer->device; + const struct radv_binning_settings *settings = &device->physical_device->binning_settings; const struct radv_dynamic_state *d = &cmd_buffer->state.dynamic; + if (device->pbb_allowed && settings->context_states_per_bin > 1) { + /* Flush DFSM on CB_TARGET_MASK changes. */ + radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); + radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0)); + } + radeon_set_context_reg(cmd_buffer->cs, R_028238_CB_TARGET_MASK, d->color_write_mask & d->color_write_enable); } @@ -8491,18 +8499,6 @@ radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer, const struct r } } - if (device->pbb_allowed) { - struct radv_binning_settings *settings = &device->physical_device->binning_settings; - - if ((cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_COLOR_WRITE_ENABLE | - RADV_CMD_DIRTY_DYNAMIC_COLOR_WRITE_MASK)) && - settings->context_states_per_bin > 1) { - /* Break the batch on CB_TARGET_MASK changes. */ - radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); - radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0)); - } - } - /* Pre-compute some tessellation info that depend on the number of patch control points when the * bound pipeline declared this state as dynamic. */