AlexIndustrial/mesa
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

intel/brw: Use enums for DPAS source regioning

Browse Source 
Was previously passing 1, 1, 0 as the regioning. This generated
incorrect disassembly because the encoding for a width of 1 is 0. Use
the enums to ensure the correct values are used.

Fixes: 1c92dad5cb ("intel/disasm: Disassembly support for DPAS")
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28404>
This commit is contained in:
Ian Romanick
2024-03-25 12:52:46 -07:00
committed by Marge Bot
parent be4fa59a72
commit c6bd6f2a41
1 changed files with 12 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/intel/compiler/brw_disasm.c
+12 -3
View File
@@ -1469,7 +1469,10 @@ src0_dpas_3src(FILE *file, const struct intel_device_info *devinfo,
if (subreg_nr)
format(file, ".%d", subreg_nr);
src_align1_region(file, 1, 1, 0);
src_align1_region(file,
BRW_VERTICAL_STRIDE_1,
BRW_WIDTH_1,
BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_0);
string(file, brw_reg_type_to_letters(type));
@@ -1490,7 +1493,10 @@ src1_dpas_3src(FILE *file, const struct intel_device_info *devinfo,
if (subreg_nr)
format(file, ".%d", subreg_nr);
src_align1_region(file, 1, 1, 0);
src_align1_region(file,
BRW_VERTICAL_STRIDE_1,
BRW_WIDTH_1,
BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_0);
string(file, brw_reg_type_to_letters(type));
@@ -1511,7 +1517,10 @@ src2_dpas_3src(FILE *file, const struct intel_device_info *devinfo,
if (subreg_nr)
format(file, ".%d", subreg_nr);
src_align1_region(file, 1, 1, 0);
src_align1_region(file,
BRW_VERTICAL_STRIDE_1,
BRW_WIDTH_1,
BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_0);
string(file, brw_reg_type_to_letters(type));