From c6bd6f2a41253e6430229e1e2ea8a969fd04363b Mon Sep 17 00:00:00 2001 From: Ian Romanick Date: Mon, 25 Mar 2024 12:52:46 -0700 Subject: [PATCH] intel/brw: Use enums for DPAS source regioning Was previously passing 1, 1, 0 as the regioning. This generated incorrect disassembly because the encoding for a width of 1 is 0. Use the enums to ensure the correct values are used. Fixes: 1c92dad5cb7 ("intel/disasm: Disassembly support for DPAS") Reviewed-by: Jordan Justen Part-of: --- src/intel/compiler/brw_disasm.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/src/intel/compiler/brw_disasm.c b/src/intel/compiler/brw_disasm.c index c28492a97e9..b68b649db9a 100644 --- a/src/intel/compiler/brw_disasm.c +++ b/src/intel/compiler/brw_disasm.c @@ -1469,7 +1469,10 @@ src0_dpas_3src(FILE *file, const struct intel_device_info *devinfo, if (subreg_nr) format(file, ".%d", subreg_nr); - src_align1_region(file, 1, 1, 0); + src_align1_region(file, + BRW_VERTICAL_STRIDE_1, + BRW_WIDTH_1, + BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_0); string(file, brw_reg_type_to_letters(type)); @@ -1490,7 +1493,10 @@ src1_dpas_3src(FILE *file, const struct intel_device_info *devinfo, if (subreg_nr) format(file, ".%d", subreg_nr); - src_align1_region(file, 1, 1, 0); + src_align1_region(file, + BRW_VERTICAL_STRIDE_1, + BRW_WIDTH_1, + BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_0); string(file, brw_reg_type_to_letters(type)); @@ -1511,7 +1517,10 @@ src2_dpas_3src(FILE *file, const struct intel_device_info *devinfo, if (subreg_nr) format(file, ".%d", subreg_nr); - src_align1_region(file, 1, 1, 0); + src_align1_region(file, + BRW_VERTICAL_STRIDE_1, + BRW_WIDTH_1, + BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_0); string(file, brw_reg_type_to_letters(type));