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ac/nir/ngg: don't use 8bit alu ops

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aco doesn't support 8bit alu ops and radeonsi won't
call nir_lower_bit_size for most alu ops, so just
don't use 8bit alu ops (they will be lowered to 32bit
anyway if we do).

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23094>
This commit is contained in:
Qiang Yu
2023-05-10 14:11:48 +08:00
committed by Marge Bot
parent 12ee7eccf7
commit c5c98d2f20
1 changed files with 1 additions and 1 deletions
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src/amd/common/ac_nir_lower_ngg.c
+1 -1
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@@ -1585,7 +1585,7 @@ add_deferred_attribute_culling(nir_builder *b, nir_cf_list *original_extracted_c
if_es_thread->control = nir_selection_control_divergent_always_taken;
{
nir_ssa_def *accepted = nir_load_shared(b, 1, 8u, es_vertex_lds_addr, .base = lds_es_vertex_accepted, .align_mul = 4u);
nir_ssa_def *accepted_bool = nir_ine(b, accepted, nir_imm_intN_t(b, 0, 8));
nir_ssa_def *accepted_bool = nir_ine(b, nir_u2u32(b, accepted), nir_imm_int(b, 0));
nir_store_var(b, s->es_accepted_var, accepted_bool, 0x1u);
}
nir_pop_if(b, if_es_thread);