From c5c98d2f20833a4d1f95af9fe2fbe09affea8200 Mon Sep 17 00:00:00 2001 From: Qiang Yu Date: Wed, 10 May 2023 14:11:48 +0800 Subject: [PATCH] ac/nir/ngg: don't use 8bit alu ops aco doesn't support 8bit alu ops and radeonsi won't call nir_lower_bit_size for most alu ops, so just don't use 8bit alu ops (they will be lowered to 32bit anyway if we do). Reviewed-by: Rhys Perry Signed-off-by: Qiang Yu Part-of: --- src/amd/common/ac_nir_lower_ngg.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/amd/common/ac_nir_lower_ngg.c b/src/amd/common/ac_nir_lower_ngg.c index c52e9db72d5..fdde4c82813 100644 --- a/src/amd/common/ac_nir_lower_ngg.c +++ b/src/amd/common/ac_nir_lower_ngg.c @@ -1585,7 +1585,7 @@ add_deferred_attribute_culling(nir_builder *b, nir_cf_list *original_extracted_c if_es_thread->control = nir_selection_control_divergent_always_taken; { nir_ssa_def *accepted = nir_load_shared(b, 1, 8u, es_vertex_lds_addr, .base = lds_es_vertex_accepted, .align_mul = 4u); - nir_ssa_def *accepted_bool = nir_ine(b, accepted, nir_imm_intN_t(b, 0, 8)); + nir_ssa_def *accepted_bool = nir_ine(b, nir_u2u32(b, accepted), nir_imm_int(b, 0)); nir_store_var(b, s->es_accepted_var, accepted_bool, 0x1u); } nir_pop_if(b, if_es_thread);