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intel/compiler: Add enum xe2_lsc_cache_store

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Rework:
 * Rohan: Fix enum value for L1WB_L3WB
 * Fix write-through comments (Ken)

Ref: bspec 71167
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>
This commit is contained in:
Jordan Justen
2022-08-05 14:18:43 -07:00
committed by Marge Bot
parent 1245020282
commit c54eff2e03
1 changed files with 28 additions and 0 deletions
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28
src/intel/compiler/brw_eu_defines.h
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@@ -1891,6 +1891,34 @@ enum ENUM_PACKED lsc_cache_store {
};
/*
* Specifies the dataport message override to the default L1 and L3 memory
* cache policies. Dataport L1 cache policies are uncached (UC), write-through
* (WT), write-back (WB) and streaming (S). Dataport L3 cache policies are
* uncached (UC) and cached (WB).
*/
enum PACKED xe2_lsc_cache_store {
/* No override. Use the non-pipelined or surface state cache settings for L1
* and L3.
*/
XE2_LSC_CACHE_STORE_L1STATE_L3MOCS = 0,
/* Override to L1 uncached and L3 uncached */
XE2_LSC_CACHE_STORE_L1UC_L3UC = 2,
/* Override to L1 uncached and L3 cached */
XE2_LSC_CACHE_STORE_L1UC_L3WB = 4,
/* Override to L1 write-through and L3 uncached */
XE2_LSC_CACHE_STORE_L1WT_L3UC = 6,
/* Override to L1 write-through and L3 cached */
XE2_LSC_CACHE_STORE_L1WT_L3WB = 8,
/* Override to L1 streaming and L3 uncached */
XE2_LSC_CACHE_STORE_L1S_L3UC = 10,
/* Override to L1 streaming and L3 cached */
XE2_LSC_CACHE_STORE_L1S_L3WB = 12,
/* Override to L1 write-back and L3 cached */
XE2_LSC_CACHE_STORE_L1WB_L3WB = 14,
};
/*
* Specifies which components of the data payload 4-element vector (X,Y,Z,W) is
* packed into the register payload.