From c54eff2e03ea8eb2ea0a62cd0e5d11d29e6c7d46 Mon Sep 17 00:00:00 2001 From: Jordan Justen Date: Fri, 5 Aug 2022 14:18:43 -0700 Subject: [PATCH] intel/compiler: Add enum xe2_lsc_cache_store Rework: * Rohan: Fix enum value for L1WB_L3WB * Fix write-through comments (Ken) Ref: bspec 71167 Signed-off-by: Jordan Justen Reviewed-by: Kenneth Graunke Part-of: --- src/intel/compiler/brw_eu_defines.h | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/src/intel/compiler/brw_eu_defines.h b/src/intel/compiler/brw_eu_defines.h index 6e8f955f2ca..aaf63c62a23 100644 --- a/src/intel/compiler/brw_eu_defines.h +++ b/src/intel/compiler/brw_eu_defines.h @@ -1891,6 +1891,34 @@ enum ENUM_PACKED lsc_cache_store { }; +/* + * Specifies the dataport message override to the default L1 and L3 memory + * cache policies. Dataport L1 cache policies are uncached (UC), write-through + * (WT), write-back (WB) and streaming (S). Dataport L3 cache policies are + * uncached (UC) and cached (WB). + */ +enum PACKED xe2_lsc_cache_store { + /* No override. Use the non-pipelined or surface state cache settings for L1 + * and L3. + */ + XE2_LSC_CACHE_STORE_L1STATE_L3MOCS = 0, + /* Override to L1 uncached and L3 uncached */ + XE2_LSC_CACHE_STORE_L1UC_L3UC = 2, + /* Override to L1 uncached and L3 cached */ + XE2_LSC_CACHE_STORE_L1UC_L3WB = 4, + /* Override to L1 write-through and L3 uncached */ + XE2_LSC_CACHE_STORE_L1WT_L3UC = 6, + /* Override to L1 write-through and L3 cached */ + XE2_LSC_CACHE_STORE_L1WT_L3WB = 8, + /* Override to L1 streaming and L3 uncached */ + XE2_LSC_CACHE_STORE_L1S_L3UC = 10, + /* Override to L1 streaming and L3 cached */ + XE2_LSC_CACHE_STORE_L1S_L3WB = 12, + /* Override to L1 write-back and L3 cached */ + XE2_LSC_CACHE_STORE_L1WB_L3WB = 14, + +}; + /* * Specifies which components of the data payload 4-element vector (X,Y,Z,W) is * packed into the register payload.